/* Automatically generated from ./jit-rules-arm.sel - DO NOT EDIT */
/*
 * Copyright (C) 2004  Southern Storm Software, Pty Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*/

#if defined(JIT_INCLUDE_RULES)

case JIT_OP_TRUNC_SBYTE:
{
	arm_inst_buf inst;
	int reg;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	{
		jit_gen_load_inst_ptr(gen, inst);
#line 28 "./jit-rules-arm.sel"
		{
			arm_shift_reg_imm8(inst, ARM_SHL, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, 24);
			arm_shift_reg_imm8(inst, ARM_SAR, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, 24);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

case JIT_OP_TRUNC_UBYTE:
{
	arm_inst_buf inst;
	int reg;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	{
		jit_gen_load_inst_ptr(gen, inst);
#line 34 "./jit-rules-arm.sel"
		{
			arm_alu_reg_imm8(inst, ARM_AND, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, 0xFF);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

case JIT_OP_TRUNC_SHORT:
{
	arm_inst_buf inst;
	int reg;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	{
		jit_gen_load_inst_ptr(gen, inst);
#line 39 "./jit-rules-arm.sel"
		{
			arm_shift_reg_imm8(inst, ARM_SHL, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, 16);
			arm_shift_reg_imm8(inst, ARM_SAR, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, 16);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

case JIT_OP_TRUNC_USHORT:
{
	arm_inst_buf inst;
	int reg;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	{
		jit_gen_load_inst_ptr(gen, inst);
#line 45 "./jit-rules-arm.sel"
		{
			arm_shift_reg_imm8(inst, ARM_SHL, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, 16);
			arm_shift_reg_imm8(inst, ARM_SHR, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, 16);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

case JIT_OP_IADD:
{
	arm_inst_buf inst;
	int reg;
	int reg2;
	jit_nint imm_value;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	if(insn->value2->is_nint_constant && insn->value2->address >= 0 && insn->value2->address <= 255)
	{
		imm_value = insn->value2->address;
		jit_gen_load_inst_ptr(gen, inst);
#line 55 "./jit-rules-arm.sel"
		{
			arm_alu_reg_imm8(inst, ARM_ADD, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, imm_value);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	else
	{
		reg2 = _jit_regs_load_value(gen, insn->value2, 0, (insn->flags & (JIT_INSN_VALUE2_NEXT_USE | JIT_INSN_VALUE2_LIVE)));
		jit_gen_load_inst_ptr(gen, inst);
#line 58 "./jit-rules-arm.sel"
		{
			arm_alu_reg_reg(inst, ARM_ADD, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg2].cpu_reg);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

case JIT_OP_ISUB:
{
	arm_inst_buf inst;
	int reg;
	int reg2;
	jit_nint imm_value;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	if(insn->value2->is_nint_constant && insn->value2->address >= 0 && insn->value2->address <= 255)
	{
		imm_value = insn->value2->address;
		jit_gen_load_inst_ptr(gen, inst);
#line 63 "./jit-rules-arm.sel"
		{
			arm_alu_reg_imm8(inst, ARM_SUB, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, imm_value);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	else
	{
		reg2 = _jit_regs_load_value(gen, insn->value2, 0, (insn->flags & (JIT_INSN_VALUE2_NEXT_USE | JIT_INSN_VALUE2_LIVE)));
		jit_gen_load_inst_ptr(gen, inst);
#line 66 "./jit-rules-arm.sel"
		{
			arm_alu_reg_reg(inst, ARM_SUB, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg2].cpu_reg);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

case JIT_OP_IMUL:
{
	arm_inst_buf inst;
	int reg;
	int reg2;
	jit_nint imm_value;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	if(insn->value2->is_nint_constant && insn->value2->address >= 0 && insn->value2->address <= 255)
	{
		imm_value = insn->value2->address;
		jit_gen_load_inst_ptr(gen, inst);
#line 71 "./jit-rules-arm.sel"
		{
			/* Handle special cases of immediate multiplies */
			switch(imm_value)
			{
				case 0:
				{
					arm_mov_reg_imm8(inst, _jit_reg_info[reg].cpu_reg, 0);
				}
				break;
	
				case 1: break;
	
				case 2:
				{
					arm_shift_reg_imm8(inst, ARM_SHL, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, 1);
				}
				break;
	
				case 4:
				{
					arm_shift_reg_imm8(inst, ARM_SHL, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, 2);
				}
				break;
	
				case 8:
				{
					arm_shift_reg_imm8(inst, ARM_SHL, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, 3);
				}
				break;
	
				case 16:
				{
					arm_shift_reg_imm8(inst, ARM_SHL, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, 4);
				}
				break;
	
				case 32:
				{
					arm_shift_reg_imm8(inst, ARM_SHL, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, 5);
				}
				break;
	
				case 64:
				{
					arm_shift_reg_imm8(inst, ARM_SHL, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, 6);
				}
				break;
	
				case 128:
				{
					arm_shift_reg_imm8(inst, ARM_SHL, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, 7);
				}
				break;
	
				default:
				{
					arm_mov_reg_imm8(inst, ARM_WORK, imm_value);
					arm_mul_reg_reg(inst, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, ARM_WORK);
				}
				break;
			}
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	else
	{
		reg2 = _jit_regs_load_value(gen, insn->value2, 0, (insn->flags & (JIT_INSN_VALUE2_NEXT_USE | JIT_INSN_VALUE2_LIVE)));
		jit_gen_load_inst_ptr(gen, inst);
#line 133 "./jit-rules-arm.sel"
		{
			if(_jit_reg_info[reg].cpu_reg != _jit_reg_info[reg2].cpu_reg)
			{
				arm_mul_reg_reg(inst, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg2].cpu_reg);
			}
			else
			{
				/* Cannot use the same register for both arguments */
				arm_mov_reg_reg(inst, ARM_WORK, _jit_reg_info[reg2].cpu_reg);
				arm_mul_reg_reg(inst, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, ARM_WORK);
			}
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

case JIT_OP_INEG:
{
	arm_inst_buf inst;
	int reg;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	{
		jit_gen_load_inst_ptr(gen, inst);
#line 147 "./jit-rules-arm.sel"
		{
			/* -x is the same as (0 - x) */
			arm_alu_reg_imm8(inst, ARM_RSB, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, 0);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

case JIT_OP_LADD:
{
	arm_inst_buf inst;
	int reg;
	int reg2;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	{
		reg2 = _jit_regs_load_value(gen, insn->value2, 0, (insn->flags & (JIT_INSN_VALUE2_NEXT_USE | JIT_INSN_VALUE2_LIVE)));
		jit_gen_load_inst_ptr(gen, inst);
#line 153 "./jit-rules-arm.sel"
		{
			arm_alu_cc_reg_reg(inst, ARM_ADD, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg2].cpu_reg);
			arm_alu_reg_reg(inst, ARM_ADC, _jit_reg_info[_jit_reg_info[reg].other_reg].cpu_reg, _jit_reg_info[_jit_reg_info[reg].other_reg].cpu_reg, _jit_reg_info[_jit_reg_info[reg2].other_reg].cpu_reg);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

case JIT_OP_LSUB:
{
	arm_inst_buf inst;
	int reg;
	int reg2;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	{
		reg2 = _jit_regs_load_value(gen, insn->value2, 0, (insn->flags & (JIT_INSN_VALUE2_NEXT_USE | JIT_INSN_VALUE2_LIVE)));
		jit_gen_load_inst_ptr(gen, inst);
#line 159 "./jit-rules-arm.sel"
		{
			arm_alu_cc_reg_reg(inst, ARM_SUB, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg2].cpu_reg);
			arm_alu_reg_reg(inst, ARM_SBC, _jit_reg_info[_jit_reg_info[reg].other_reg].cpu_reg, _jit_reg_info[_jit_reg_info[reg].other_reg].cpu_reg, _jit_reg_info[_jit_reg_info[reg2].other_reg].cpu_reg);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

case JIT_OP_LNEG:
{
	arm_inst_buf inst;
	int reg;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	{
		jit_gen_load_inst_ptr(gen, inst);
#line 165 "./jit-rules-arm.sel"
		{
			arm_alu_reg(inst, ARM_MVN, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg);
			arm_alu_reg(inst, ARM_MVN, _jit_reg_info[_jit_reg_info[reg].other_reg].cpu_reg, _jit_reg_info[_jit_reg_info[reg].other_reg].cpu_reg);
			arm_alu_cc_reg_imm8(inst, ARM_ADD, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, 1);
			arm_alu_reg_imm8(inst, ARM_ADC, _jit_reg_info[_jit_reg_info[reg].other_reg].cpu_reg, _jit_reg_info[_jit_reg_info[reg].other_reg].cpu_reg, 0);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

#ifdef JIT_ARM_HAS_FLOAT_REGS

case JIT_OP_FADD:
{
	arm_inst_buf inst;
	int reg;
	int reg2;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	{
		reg2 = _jit_regs_load_value(gen, insn->value2, 0, (insn->flags & (JIT_INSN_VALUE2_NEXT_USE | JIT_INSN_VALUE2_LIVE)));
		jit_gen_load_inst_ptr(gen, inst);
#line 173 "./jit-rules-arm.sel"
		{
			arm_alu_freg_freg_32(inst, ARM_ADF, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg2].cpu_reg);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

#endif /* JIT_ARM_HAS_FLOAT_REGS */

#ifdef JIT_ARM_HAS_FLOAT_REGS

case JIT_OP_FSUB:
{
	arm_inst_buf inst;
	int reg;
	int reg2;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	{
		reg2 = _jit_regs_load_value(gen, insn->value2, 0, (insn->flags & (JIT_INSN_VALUE2_NEXT_USE | JIT_INSN_VALUE2_LIVE)));
		jit_gen_load_inst_ptr(gen, inst);
#line 178 "./jit-rules-arm.sel"
		{
			arm_alu_freg_freg_32(inst, ARM_SUF, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg2].cpu_reg);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

#endif /* JIT_ARM_HAS_FLOAT_REGS */

#ifdef JIT_ARM_HAS_FLOAT_REGS

case JIT_OP_FMUL:
{
	arm_inst_buf inst;
	int reg;
	int reg2;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	{
		reg2 = _jit_regs_load_value(gen, insn->value2, 0, (insn->flags & (JIT_INSN_VALUE2_NEXT_USE | JIT_INSN_VALUE2_LIVE)));
		jit_gen_load_inst_ptr(gen, inst);
#line 183 "./jit-rules-arm.sel"
		{
			arm_alu_freg_freg_32(inst, ARM_MUF, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg2].cpu_reg);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

#endif /* JIT_ARM_HAS_FLOAT_REGS */

#ifdef JIT_ARM_HAS_FLOAT_REGS

case JIT_OP_FDIV:
{
	arm_inst_buf inst;
	int reg;
	int reg2;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	{
		reg2 = _jit_regs_load_value(gen, insn->value2, 0, (insn->flags & (JIT_INSN_VALUE2_NEXT_USE | JIT_INSN_VALUE2_LIVE)));
		jit_gen_load_inst_ptr(gen, inst);
#line 188 "./jit-rules-arm.sel"
		{
			arm_alu_freg_freg_32(inst, ARM_DVF, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg2].cpu_reg);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

#endif /* JIT_ARM_HAS_FLOAT_REGS */

#ifdef JIT_ARM_HAS_FLOAT_REGS

case JIT_OP_FNEG:
{
	arm_inst_buf inst;
	int reg;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	{
		jit_gen_load_inst_ptr(gen, inst);
#line 193 "./jit-rules-arm.sel"
		{
			arm_alu_freg_32(inst, ARM_MNF, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

#endif /* JIT_ARM_HAS_FLOAT_REGS */

#ifdef JIT_ARM_HAS_FLOAT_REGS

case JIT_OP_DADD:
case JIT_OP_NFADD:
{
	arm_inst_buf inst;
	int reg;
	int reg2;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	{
		reg2 = _jit_regs_load_value(gen, insn->value2, 0, (insn->flags & (JIT_INSN_VALUE2_NEXT_USE | JIT_INSN_VALUE2_LIVE)));
		jit_gen_load_inst_ptr(gen, inst);
#line 198 "./jit-rules-arm.sel"
		{
			arm_alu_freg_freg(inst, ARM_ADF, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg2].cpu_reg);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

#endif /* JIT_ARM_HAS_FLOAT_REGS */

#ifdef JIT_ARM_HAS_FLOAT_REGS

case JIT_OP_DSUB:
case JIT_OP_NFSUB:
{
	arm_inst_buf inst;
	int reg;
	int reg2;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	{
		reg2 = _jit_regs_load_value(gen, insn->value2, 0, (insn->flags & (JIT_INSN_VALUE2_NEXT_USE | JIT_INSN_VALUE2_LIVE)));
		jit_gen_load_inst_ptr(gen, inst);
#line 203 "./jit-rules-arm.sel"
		{
			arm_alu_freg_freg(inst, ARM_SUF, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg2].cpu_reg);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

#endif /* JIT_ARM_HAS_FLOAT_REGS */

#ifdef JIT_ARM_HAS_FLOAT_REGS

case JIT_OP_DMUL:
case JIT_OP_NFMUL:
{
	arm_inst_buf inst;
	int reg;
	int reg2;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	{
		reg2 = _jit_regs_load_value(gen, insn->value2, 0, (insn->flags & (JIT_INSN_VALUE2_NEXT_USE | JIT_INSN_VALUE2_LIVE)));
		jit_gen_load_inst_ptr(gen, inst);
#line 208 "./jit-rules-arm.sel"
		{
			arm_alu_freg_freg(inst, ARM_MUF, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg2].cpu_reg);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

#endif /* JIT_ARM_HAS_FLOAT_REGS */

#ifdef JIT_ARM_HAS_FLOAT_REGS

case JIT_OP_DDIV:
case JIT_OP_NFDIV:
{
	arm_inst_buf inst;
	int reg;
	int reg2;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	{
		reg2 = _jit_regs_load_value(gen, insn->value2, 0, (insn->flags & (JIT_INSN_VALUE2_NEXT_USE | JIT_INSN_VALUE2_LIVE)));
		jit_gen_load_inst_ptr(gen, inst);
#line 213 "./jit-rules-arm.sel"
		{
			arm_alu_freg_freg(inst, ARM_DVF, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg2].cpu_reg);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

#endif /* JIT_ARM_HAS_FLOAT_REGS */

#ifdef JIT_ARM_HAS_FLOAT_REGS

case JIT_OP_DNEG:
case JIT_OP_NFNEG:
{
	arm_inst_buf inst;
	int reg;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	{
		jit_gen_load_inst_ptr(gen, inst);
#line 218 "./jit-rules-arm.sel"
		{
			arm_alu_freg(inst, ARM_MNF, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

#endif /* JIT_ARM_HAS_FLOAT_REGS */

case JIT_OP_IAND:
{
	arm_inst_buf inst;
	int reg;
	int reg2;
	jit_nint imm_value;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	if(insn->value2->is_nint_constant && insn->value2->address >= 0 && insn->value2->address <= 255)
	{
		imm_value = insn->value2->address;
		jit_gen_load_inst_ptr(gen, inst);
#line 227 "./jit-rules-arm.sel"
		{
			arm_alu_reg_imm8(inst, ARM_AND, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, imm_value);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	else
	{
		reg2 = _jit_regs_load_value(gen, insn->value2, 0, (insn->flags & (JIT_INSN_VALUE2_NEXT_USE | JIT_INSN_VALUE2_LIVE)));
		jit_gen_load_inst_ptr(gen, inst);
#line 230 "./jit-rules-arm.sel"
		{
			arm_alu_reg_reg(inst, ARM_AND, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg2].cpu_reg);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

case JIT_OP_IOR:
{
	arm_inst_buf inst;
	int reg;
	int reg2;
	jit_nint imm_value;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	if(insn->value2->is_nint_constant && insn->value2->address >= 0 && insn->value2->address <= 255)
	{
		imm_value = insn->value2->address;
		jit_gen_load_inst_ptr(gen, inst);
#line 235 "./jit-rules-arm.sel"
		{
			arm_alu_reg_imm8(inst, ARM_ORR, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, imm_value);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	else
	{
		reg2 = _jit_regs_load_value(gen, insn->value2, 0, (insn->flags & (JIT_INSN_VALUE2_NEXT_USE | JIT_INSN_VALUE2_LIVE)));
		jit_gen_load_inst_ptr(gen, inst);
#line 238 "./jit-rules-arm.sel"
		{
			arm_alu_reg_reg(inst, ARM_ORR, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg2].cpu_reg);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

case JIT_OP_IXOR:
{
	arm_inst_buf inst;
	int reg;
	int reg2;
	jit_nint imm_value;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	if(insn->value2->is_nint_constant && insn->value2->address >= 0 && insn->value2->address <= 255)
	{
		imm_value = insn->value2->address;
		jit_gen_load_inst_ptr(gen, inst);
#line 243 "./jit-rules-arm.sel"
		{
			arm_alu_reg_imm8(inst, ARM_EOR, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, imm_value);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	else
	{
		reg2 = _jit_regs_load_value(gen, insn->value2, 0, (insn->flags & (JIT_INSN_VALUE2_NEXT_USE | JIT_INSN_VALUE2_LIVE)));
		jit_gen_load_inst_ptr(gen, inst);
#line 246 "./jit-rules-arm.sel"
		{
			arm_alu_reg_reg(inst, ARM_EOR, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg2].cpu_reg);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

case JIT_OP_INOT:
{
	arm_inst_buf inst;
	int reg;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	{
		jit_gen_load_inst_ptr(gen, inst);
#line 251 "./jit-rules-arm.sel"
		{
			/* MVN == "move not" */
			arm_alu_reg(inst, ARM_MVN, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

case JIT_OP_ISHL:
{
	arm_inst_buf inst;
	int reg;
	int reg2;
	jit_nint imm_value;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	if(insn->value2->is_constant)
	{
		imm_value = insn->value2->address;
		jit_gen_load_inst_ptr(gen, inst);
#line 257 "./jit-rules-arm.sel"
		{
			arm_shift_reg_imm8(inst, ARM_SHL, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, (imm_value & 0x1F));
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	else
	{
		reg2 = _jit_regs_load_value(gen, insn->value2, 0, (insn->flags & (JIT_INSN_VALUE2_NEXT_USE | JIT_INSN_VALUE2_LIVE)));
		jit_gen_load_inst_ptr(gen, inst);
#line 260 "./jit-rules-arm.sel"
		{
			arm_alu_reg_imm8(inst, ARM_AND, ARM_WORK, _jit_reg_info[reg2].cpu_reg, 0x1F);
			arm_shift_reg_reg(inst, ARM_SHL, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, ARM_WORK);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

case JIT_OP_ISHR:
{
	arm_inst_buf inst;
	int reg;
	int reg2;
	jit_nint imm_value;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	if(insn->value2->is_constant)
	{
		imm_value = insn->value2->address;
		jit_gen_load_inst_ptr(gen, inst);
#line 266 "./jit-rules-arm.sel"
		{
			arm_shift_reg_imm8(inst, ARM_SAR, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, (imm_value & 0x1F));
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	else
	{
		reg2 = _jit_regs_load_value(gen, insn->value2, 0, (insn->flags & (JIT_INSN_VALUE2_NEXT_USE | JIT_INSN_VALUE2_LIVE)));
		jit_gen_load_inst_ptr(gen, inst);
#line 269 "./jit-rules-arm.sel"
		{
			arm_alu_reg_imm8(inst, ARM_AND, ARM_WORK, _jit_reg_info[reg2].cpu_reg, 0x1F);
			arm_shift_reg_reg(inst, ARM_SAR, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, ARM_WORK);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

case JIT_OP_ISHR_UN:
{
	arm_inst_buf inst;
	int reg;
	int reg2;
	jit_nint imm_value;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	if(insn->value2->is_constant)
	{
		imm_value = insn->value2->address;
		jit_gen_load_inst_ptr(gen, inst);
#line 275 "./jit-rules-arm.sel"
		{
			arm_shift_reg_imm8(inst, ARM_SHR, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, (imm_value & 0x1F));
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	else
	{
		reg2 = _jit_regs_load_value(gen, insn->value2, 0, (insn->flags & (JIT_INSN_VALUE2_NEXT_USE | JIT_INSN_VALUE2_LIVE)));
		jit_gen_load_inst_ptr(gen, inst);
#line 278 "./jit-rules-arm.sel"
		{
			arm_alu_reg_imm8(inst, ARM_AND, ARM_WORK, _jit_reg_info[reg2].cpu_reg, 0x1F);
			arm_shift_reg_reg(inst, ARM_SHR, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, ARM_WORK);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

case JIT_OP_LAND:
{
	arm_inst_buf inst;
	int reg;
	int reg2;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	{
		reg2 = _jit_regs_load_value(gen, insn->value2, 0, (insn->flags & (JIT_INSN_VALUE2_NEXT_USE | JIT_INSN_VALUE2_LIVE)));
		jit_gen_load_inst_ptr(gen, inst);
#line 284 "./jit-rules-arm.sel"
		{
			arm_alu_reg_reg(inst, ARM_AND, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg2].cpu_reg);
			arm_alu_reg_reg(inst, ARM_AND, _jit_reg_info[_jit_reg_info[reg].other_reg].cpu_reg, _jit_reg_info[_jit_reg_info[reg].other_reg].cpu_reg, _jit_reg_info[_jit_reg_info[reg2].other_reg].cpu_reg);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

case JIT_OP_LOR:
{
	arm_inst_buf inst;
	int reg;
	int reg2;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	{
		reg2 = _jit_regs_load_value(gen, insn->value2, 0, (insn->flags & (JIT_INSN_VALUE2_NEXT_USE | JIT_INSN_VALUE2_LIVE)));
		jit_gen_load_inst_ptr(gen, inst);
#line 290 "./jit-rules-arm.sel"
		{
			arm_alu_reg_reg(inst, ARM_ORR, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg2].cpu_reg);
			arm_alu_reg_reg(inst, ARM_ORR, _jit_reg_info[_jit_reg_info[reg].other_reg].cpu_reg, _jit_reg_info[_jit_reg_info[reg].other_reg].cpu_reg, _jit_reg_info[_jit_reg_info[reg2].other_reg].cpu_reg);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

case JIT_OP_LXOR:
{
	arm_inst_buf inst;
	int reg;
	int reg2;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	{
		reg2 = _jit_regs_load_value(gen, insn->value2, 0, (insn->flags & (JIT_INSN_VALUE2_NEXT_USE | JIT_INSN_VALUE2_LIVE)));
		jit_gen_load_inst_ptr(gen, inst);
#line 296 "./jit-rules-arm.sel"
		{
			arm_alu_reg_reg(inst, ARM_EOR, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg2].cpu_reg);
			arm_alu_reg_reg(inst, ARM_EOR, _jit_reg_info[_jit_reg_info[reg].other_reg].cpu_reg, _jit_reg_info[_jit_reg_info[reg].other_reg].cpu_reg, _jit_reg_info[_jit_reg_info[reg2].other_reg].cpu_reg);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

case JIT_OP_LNOT:
{
	arm_inst_buf inst;
	int reg;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	{
		jit_gen_load_inst_ptr(gen, inst);
#line 302 "./jit-rules-arm.sel"
		{
			arm_alu_reg(inst, ARM_MVN, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg);
			arm_alu_reg(inst, ARM_MVN, _jit_reg_info[_jit_reg_info[reg].other_reg].cpu_reg, _jit_reg_info[_jit_reg_info[reg].other_reg].cpu_reg);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

case JIT_OP_BR:
{
	arm_inst_buf inst;
	_jit_regs_spill_all(gen);
	{
		jit_gen_load_inst_ptr(gen, inst);
#line 312 "./jit-rules-arm.sel"
		{
			/* ARM_CC_AL == "always branch" */
			output_branch(func, &inst, ARM_CC_AL, insn);
	
			/* Flush the constant pool now, to minimize the probability that
			   it is accidentally flushed in the middle of a loop body */
			jit_gen_save_inst_ptr(gen, inst);
			flush_constants(gen, 1);
			jit_gen_load_inst_ptr(gen, inst);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
}
break;

case JIT_OP_BR_IFALSE:
{
	arm_inst_buf inst;
	int reg;
	reg = _jit_regs_load_value(gen, insn->value1, 0, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	{
		_jit_regs_spill_all(gen);
		jit_gen_load_inst_ptr(gen, inst);
#line 324 "./jit-rules-arm.sel"
		{
			arm_test_reg_imm8(inst, ARM_CMP, _jit_reg_info[reg].cpu_reg, 0);
			output_branch(func, &inst, ARM_CC_EQ, insn);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
}
break;

case JIT_OP_BR_ITRUE:
{
	arm_inst_buf inst;
	int reg;
	reg = _jit_regs_load_value(gen, insn->value1, 0, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	{
		_jit_regs_spill_all(gen);
		jit_gen_load_inst_ptr(gen, inst);
#line 330 "./jit-rules-arm.sel"
		{
			arm_test_reg_imm8(inst, ARM_CMP, _jit_reg_info[reg].cpu_reg, 0);
			output_branch(func, &inst, ARM_CC_NE, insn);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
}
break;

case JIT_OP_BR_IEQ:
{
	arm_inst_buf inst;
	int reg;
	int reg2;
	jit_nint imm_value;
	reg = _jit_regs_load_value(gen, insn->value1, 0, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	if(insn->value2->is_nint_constant && insn->value2->address >= 0 && insn->value2->address <= 255)
	{
		imm_value = insn->value2->address;
		_jit_regs_spill_all(gen);
		jit_gen_load_inst_ptr(gen, inst);
#line 336 "./jit-rules-arm.sel"
		{
			arm_test_reg_imm8(inst, ARM_CMP, _jit_reg_info[reg].cpu_reg, imm_value);
			output_branch(func, &inst, ARM_CC_EQ, insn);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	else
	{
		reg2 = _jit_regs_load_value(gen, insn->value2, 0, (insn->flags & (JIT_INSN_VALUE2_NEXT_USE | JIT_INSN_VALUE2_LIVE)));
		_jit_regs_spill_all(gen);
		jit_gen_load_inst_ptr(gen, inst);
#line 340 "./jit-rules-arm.sel"
		{
			arm_test_reg_reg(inst, ARM_CMP, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg2].cpu_reg);
			output_branch(func, &inst, ARM_CC_EQ, insn);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
}
break;

case JIT_OP_BR_INE:
{
	arm_inst_buf inst;
	int reg;
	int reg2;
	jit_nint imm_value;
	reg = _jit_regs_load_value(gen, insn->value1, 0, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	if(insn->value2->is_nint_constant && insn->value2->address >= 0 && insn->value2->address <= 255)
	{
		imm_value = insn->value2->address;
		_jit_regs_spill_all(gen);
		jit_gen_load_inst_ptr(gen, inst);
#line 346 "./jit-rules-arm.sel"
		{
			arm_test_reg_imm8(inst, ARM_CMP, _jit_reg_info[reg].cpu_reg, imm_value);
			output_branch(func, &inst, ARM_CC_NE, insn);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	else
	{
		reg2 = _jit_regs_load_value(gen, insn->value2, 0, (insn->flags & (JIT_INSN_VALUE2_NEXT_USE | JIT_INSN_VALUE2_LIVE)));
		_jit_regs_spill_all(gen);
		jit_gen_load_inst_ptr(gen, inst);
#line 350 "./jit-rules-arm.sel"
		{
			arm_test_reg_reg(inst, ARM_CMP, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg2].cpu_reg);
			output_branch(func, &inst, ARM_CC_NE, insn);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
}
break;

case JIT_OP_BR_ILT:
{
	arm_inst_buf inst;
	int reg;
	int reg2;
	jit_nint imm_value;
	reg = _jit_regs_load_value(gen, insn->value1, 0, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	if(insn->value2->is_nint_constant && insn->value2->address >= 0 && insn->value2->address <= 255)
	{
		imm_value = insn->value2->address;
		_jit_regs_spill_all(gen);
		jit_gen_load_inst_ptr(gen, inst);
#line 356 "./jit-rules-arm.sel"
		{
			arm_test_reg_imm8(inst, ARM_CMP, _jit_reg_info[reg].cpu_reg, imm_value);
			output_branch(func, &inst, ARM_CC_LT, insn);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	else
	{
		reg2 = _jit_regs_load_value(gen, insn->value2, 0, (insn->flags & (JIT_INSN_VALUE2_NEXT_USE | JIT_INSN_VALUE2_LIVE)));
		_jit_regs_spill_all(gen);
		jit_gen_load_inst_ptr(gen, inst);
#line 360 "./jit-rules-arm.sel"
		{
			arm_test_reg_reg(inst, ARM_CMP, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg2].cpu_reg);
			output_branch(func, &inst, ARM_CC_LT, insn);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
}
break;

case JIT_OP_BR_ILT_UN:
{
	arm_inst_buf inst;
	int reg;
	int reg2;
	jit_nint imm_value;
	reg = _jit_regs_load_value(gen, insn->value1, 0, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	if(insn->value2->is_nint_constant && insn->value2->address >= 0 && insn->value2->address <= 255)
	{
		imm_value = insn->value2->address;
		_jit_regs_spill_all(gen);
		jit_gen_load_inst_ptr(gen, inst);
#line 366 "./jit-rules-arm.sel"
		{
			arm_test_reg_imm8(inst, ARM_CMP, _jit_reg_info[reg].cpu_reg, imm_value);
			output_branch(func, &inst, ARM_CC_LT_UN, insn);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	else
	{
		reg2 = _jit_regs_load_value(gen, insn->value2, 0, (insn->flags & (JIT_INSN_VALUE2_NEXT_USE | JIT_INSN_VALUE2_LIVE)));
		_jit_regs_spill_all(gen);
		jit_gen_load_inst_ptr(gen, inst);
#line 370 "./jit-rules-arm.sel"
		{
			arm_test_reg_reg(inst, ARM_CMP, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg2].cpu_reg);
			output_branch(func, &inst, ARM_CC_LT_UN, insn);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
}
break;

case JIT_OP_BR_ILE:
{
	arm_inst_buf inst;
	int reg;
	int reg2;
	jit_nint imm_value;
	reg = _jit_regs_load_value(gen, insn->value1, 0, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	if(insn->value2->is_nint_constant && insn->value2->address >= 0 && insn->value2->address <= 255)
	{
		imm_value = insn->value2->address;
		_jit_regs_spill_all(gen);
		jit_gen_load_inst_ptr(gen, inst);
#line 376 "./jit-rules-arm.sel"
		{
			arm_test_reg_imm8(inst, ARM_CMP, _jit_reg_info[reg].cpu_reg, imm_value);
			output_branch(func, &inst, ARM_CC_LE, insn);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	else
	{
		reg2 = _jit_regs_load_value(gen, insn->value2, 0, (insn->flags & (JIT_INSN_VALUE2_NEXT_USE | JIT_INSN_VALUE2_LIVE)));
		_jit_regs_spill_all(gen);
		jit_gen_load_inst_ptr(gen, inst);
#line 380 "./jit-rules-arm.sel"
		{
			arm_test_reg_reg(inst, ARM_CMP, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg2].cpu_reg);
			output_branch(func, &inst, ARM_CC_LE, insn);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
}
break;

case JIT_OP_BR_ILE_UN:
{
	arm_inst_buf inst;
	int reg;
	int reg2;
	jit_nint imm_value;
	reg = _jit_regs_load_value(gen, insn->value1, 0, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	if(insn->value2->is_nint_constant && insn->value2->address >= 0 && insn->value2->address <= 255)
	{
		imm_value = insn->value2->address;
		_jit_regs_spill_all(gen);
		jit_gen_load_inst_ptr(gen, inst);
#line 386 "./jit-rules-arm.sel"
		{
			arm_test_reg_imm8(inst, ARM_CMP, _jit_reg_info[reg].cpu_reg, imm_value);
			output_branch(func, &inst, ARM_CC_LE_UN, insn);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	else
	{
		reg2 = _jit_regs_load_value(gen, insn->value2, 0, (insn->flags & (JIT_INSN_VALUE2_NEXT_USE | JIT_INSN_VALUE2_LIVE)));
		_jit_regs_spill_all(gen);
		jit_gen_load_inst_ptr(gen, inst);
#line 390 "./jit-rules-arm.sel"
		{
			arm_test_reg_reg(inst, ARM_CMP, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg2].cpu_reg);
			output_branch(func, &inst, ARM_CC_LE_UN, insn);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
}
break;

case JIT_OP_BR_IGT:
{
	arm_inst_buf inst;
	int reg;
	int reg2;
	jit_nint imm_value;
	reg = _jit_regs_load_value(gen, insn->value1, 0, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	if(insn->value2->is_nint_constant && insn->value2->address >= 0 && insn->value2->address <= 255)
	{
		imm_value = insn->value2->address;
		_jit_regs_spill_all(gen);
		jit_gen_load_inst_ptr(gen, inst);
#line 396 "./jit-rules-arm.sel"
		{
			arm_test_reg_imm8(inst, ARM_CMP, _jit_reg_info[reg].cpu_reg, imm_value);
			output_branch(func, &inst, ARM_CC_GT, insn);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	else
	{
		reg2 = _jit_regs_load_value(gen, insn->value2, 0, (insn->flags & (JIT_INSN_VALUE2_NEXT_USE | JIT_INSN_VALUE2_LIVE)));
		_jit_regs_spill_all(gen);
		jit_gen_load_inst_ptr(gen, inst);
#line 400 "./jit-rules-arm.sel"
		{
			arm_test_reg_reg(inst, ARM_CMP, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg2].cpu_reg);
			output_branch(func, &inst, ARM_CC_GT, insn);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
}
break;

case JIT_OP_BR_IGT_UN:
{
	arm_inst_buf inst;
	int reg;
	int reg2;
	jit_nint imm_value;
	reg = _jit_regs_load_value(gen, insn->value1, 0, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	if(insn->value2->is_nint_constant && insn->value2->address >= 0 && insn->value2->address <= 255)
	{
		imm_value = insn->value2->address;
		_jit_regs_spill_all(gen);
		jit_gen_load_inst_ptr(gen, inst);
#line 406 "./jit-rules-arm.sel"
		{
			arm_test_reg_imm8(inst, ARM_CMP, _jit_reg_info[reg].cpu_reg, imm_value);
			output_branch(func, &inst, ARM_CC_GT_UN, insn);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	else
	{
		reg2 = _jit_regs_load_value(gen, insn->value2, 0, (insn->flags & (JIT_INSN_VALUE2_NEXT_USE | JIT_INSN_VALUE2_LIVE)));
		_jit_regs_spill_all(gen);
		jit_gen_load_inst_ptr(gen, inst);
#line 410 "./jit-rules-arm.sel"
		{
			arm_test_reg_reg(inst, ARM_CMP, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg2].cpu_reg);
			output_branch(func, &inst, ARM_CC_GT_UN, insn);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
}
break;

case JIT_OP_BR_IGE:
{
	arm_inst_buf inst;
	int reg;
	int reg2;
	jit_nint imm_value;
	reg = _jit_regs_load_value(gen, insn->value1, 0, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	if(insn->value2->is_nint_constant && insn->value2->address >= 0 && insn->value2->address <= 255)
	{
		imm_value = insn->value2->address;
		_jit_regs_spill_all(gen);
		jit_gen_load_inst_ptr(gen, inst);
#line 416 "./jit-rules-arm.sel"
		{
			arm_test_reg_imm8(inst, ARM_CMP, _jit_reg_info[reg].cpu_reg, imm_value);
			output_branch(func, &inst, ARM_CC_GE, insn);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	else
	{
		reg2 = _jit_regs_load_value(gen, insn->value2, 0, (insn->flags & (JIT_INSN_VALUE2_NEXT_USE | JIT_INSN_VALUE2_LIVE)));
		_jit_regs_spill_all(gen);
		jit_gen_load_inst_ptr(gen, inst);
#line 420 "./jit-rules-arm.sel"
		{
			arm_test_reg_reg(inst, ARM_CMP, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg2].cpu_reg);
			output_branch(func, &inst, ARM_CC_GE, insn);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
}
break;

case JIT_OP_BR_IGE_UN:
{
	arm_inst_buf inst;
	int reg;
	int reg2;
	jit_nint imm_value;
	reg = _jit_regs_load_value(gen, insn->value1, 0, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	if(insn->value2->is_nint_constant && insn->value2->address >= 0 && insn->value2->address <= 255)
	{
		imm_value = insn->value2->address;
		_jit_regs_spill_all(gen);
		jit_gen_load_inst_ptr(gen, inst);
#line 426 "./jit-rules-arm.sel"
		{
			arm_test_reg_imm8(inst, ARM_CMP, _jit_reg_info[reg].cpu_reg, imm_value);
			output_branch(func, &inst, ARM_CC_GE_UN, insn);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	else
	{
		reg2 = _jit_regs_load_value(gen, insn->value2, 0, (insn->flags & (JIT_INSN_VALUE2_NEXT_USE | JIT_INSN_VALUE2_LIVE)));
		_jit_regs_spill_all(gen);
		jit_gen_load_inst_ptr(gen, inst);
#line 430 "./jit-rules-arm.sel"
		{
			arm_test_reg_reg(inst, ARM_CMP, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg2].cpu_reg);
			output_branch(func, &inst, ARM_CC_GE_UN, insn);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
}
break;

case JIT_OP_ICMP:
{
	arm_inst_buf inst;
	int reg;
	int reg2;
	jit_nint imm_value;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	if(insn->value2->is_nint_constant && insn->value2->address >= 0 && insn->value2->address <= 255)
	{
		imm_value = insn->value2->address;
		jit_gen_load_inst_ptr(gen, inst);
#line 440 "./jit-rules-arm.sel"
		{
			arm_test_reg_imm8(inst, ARM_CMP, _jit_reg_info[reg].cpu_reg, imm_value);
			arm_alu_reg_imm8_cond(inst, ARM_MOV, _jit_reg_info[reg].cpu_reg, 0, 1, ARM_CC_GT);
			arm_alu_reg_imm8_cond(inst, ARM_MOV, _jit_reg_info[reg].cpu_reg, 0, 0, ARM_CC_LE);
			arm_alu_reg_cond(inst, ARM_MVN, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, ARM_CC_LT);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	else
	{
		reg2 = _jit_regs_load_value(gen, insn->value2, 0, (insn->flags & (JIT_INSN_VALUE2_NEXT_USE | JIT_INSN_VALUE2_LIVE)));
		jit_gen_load_inst_ptr(gen, inst);
#line 446 "./jit-rules-arm.sel"
		{
			arm_test_reg_reg(inst, ARM_CMP, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg2].cpu_reg);
			arm_alu_reg_imm8_cond(inst, ARM_MOV, _jit_reg_info[reg].cpu_reg, 0, 1, ARM_CC_GT);
			arm_alu_reg_imm8_cond(inst, ARM_MOV, _jit_reg_info[reg].cpu_reg, 0, 0, ARM_CC_LE);
			arm_alu_reg_cond(inst, ARM_MVN, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, ARM_CC_LT);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

case JIT_OP_ICMP_UN:
{
	arm_inst_buf inst;
	int reg;
	int reg2;
	jit_nint imm_value;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	if(insn->value2->is_nint_constant && insn->value2->address >= 0 && insn->value2->address <= 255)
	{
		imm_value = insn->value2->address;
		jit_gen_load_inst_ptr(gen, inst);
#line 454 "./jit-rules-arm.sel"
		{
			arm_test_reg_imm8(inst, ARM_CMP, _jit_reg_info[reg].cpu_reg, imm_value);
			arm_alu_reg_imm8_cond(inst, ARM_MOV, _jit_reg_info[reg].cpu_reg, 0, 1, ARM_CC_GT_UN);
			arm_alu_reg_imm8_cond(inst, ARM_MOV, _jit_reg_info[reg].cpu_reg, 0, 0, ARM_CC_LE_UN);
			arm_alu_reg_cond(inst, ARM_MVN, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, ARM_CC_LT_UN);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	else
	{
		reg2 = _jit_regs_load_value(gen, insn->value2, 0, (insn->flags & (JIT_INSN_VALUE2_NEXT_USE | JIT_INSN_VALUE2_LIVE)));
		jit_gen_load_inst_ptr(gen, inst);
#line 460 "./jit-rules-arm.sel"
		{
			arm_test_reg_reg(inst, ARM_CMP, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg2].cpu_reg);
			arm_alu_reg_imm8_cond(inst, ARM_MOV, _jit_reg_info[reg].cpu_reg, 0, 1, ARM_CC_GT_UN);
			arm_alu_reg_imm8_cond(inst, ARM_MOV, _jit_reg_info[reg].cpu_reg, 0, 0, ARM_CC_LE_UN);
			arm_alu_reg_cond(inst, ARM_MVN, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, ARM_CC_LT_UN);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

case JIT_OP_IEQ:
{
	arm_inst_buf inst;
	int reg;
	int reg2;
	jit_nint imm_value;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	if(insn->value2->is_nint_constant && insn->value2->address >= 0 && insn->value2->address <= 255)
	{
		imm_value = insn->value2->address;
		jit_gen_load_inst_ptr(gen, inst);
#line 468 "./jit-rules-arm.sel"
		{
			arm_test_reg_imm8(inst, ARM_CMP, _jit_reg_info[reg].cpu_reg, imm_value);
			arm_alu_reg_imm8_cond(inst, ARM_MOV, _jit_reg_info[reg].cpu_reg, 0, 1, ARM_CC_EQ);
			arm_alu_reg_imm8_cond(inst, ARM_MOV, _jit_reg_info[reg].cpu_reg, 0, 0, ARM_CC_NE);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	else
	{
		reg2 = _jit_regs_load_value(gen, insn->value2, 0, (insn->flags & (JIT_INSN_VALUE2_NEXT_USE | JIT_INSN_VALUE2_LIVE)));
		jit_gen_load_inst_ptr(gen, inst);
#line 473 "./jit-rules-arm.sel"
		{
			arm_test_reg_reg(inst, ARM_CMP, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg2].cpu_reg);
			arm_alu_reg_imm8_cond(inst, ARM_MOV, _jit_reg_info[reg].cpu_reg, 0, 1, ARM_CC_EQ);
			arm_alu_reg_imm8_cond(inst, ARM_MOV, _jit_reg_info[reg].cpu_reg, 0, 0, ARM_CC_NE);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

case JIT_OP_INE:
{
	arm_inst_buf inst;
	int reg;
	int reg2;
	jit_nint imm_value;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	if(insn->value2->is_nint_constant && insn->value2->address >= 0 && insn->value2->address <= 255)
	{
		imm_value = insn->value2->address;
		jit_gen_load_inst_ptr(gen, inst);
#line 480 "./jit-rules-arm.sel"
		{
			arm_test_reg_imm8(inst, ARM_CMP, _jit_reg_info[reg].cpu_reg, imm_value);
			arm_alu_reg_imm8_cond(inst, ARM_MOV, _jit_reg_info[reg].cpu_reg, 0, 1, ARM_CC_NE);
			arm_alu_reg_imm8_cond(inst, ARM_MOV, _jit_reg_info[reg].cpu_reg, 0, 0, ARM_CC_EQ);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	else
	{
		reg2 = _jit_regs_load_value(gen, insn->value2, 0, (insn->flags & (JIT_INSN_VALUE2_NEXT_USE | JIT_INSN_VALUE2_LIVE)));
		jit_gen_load_inst_ptr(gen, inst);
#line 485 "./jit-rules-arm.sel"
		{
			arm_test_reg_reg(inst, ARM_CMP, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg2].cpu_reg);
			arm_alu_reg_imm8_cond(inst, ARM_MOV, _jit_reg_info[reg].cpu_reg, 0, 1, ARM_CC_NE);
			arm_alu_reg_imm8_cond(inst, ARM_MOV, _jit_reg_info[reg].cpu_reg, 0, 0, ARM_CC_EQ);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

case JIT_OP_ILT:
{
	arm_inst_buf inst;
	int reg;
	int reg2;
	jit_nint imm_value;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	if(insn->value2->is_nint_constant && insn->value2->address >= 0 && insn->value2->address <= 255)
	{
		imm_value = insn->value2->address;
		jit_gen_load_inst_ptr(gen, inst);
#line 492 "./jit-rules-arm.sel"
		{
			arm_test_reg_imm8(inst, ARM_CMP, _jit_reg_info[reg].cpu_reg, imm_value);
			arm_alu_reg_imm8_cond(inst, ARM_MOV, _jit_reg_info[reg].cpu_reg, 0, 1, ARM_CC_LT);
			arm_alu_reg_imm8_cond(inst, ARM_MOV, _jit_reg_info[reg].cpu_reg, 0, 0, ARM_CC_GE);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	else
	{
		reg2 = _jit_regs_load_value(gen, insn->value2, 0, (insn->flags & (JIT_INSN_VALUE2_NEXT_USE | JIT_INSN_VALUE2_LIVE)));
		jit_gen_load_inst_ptr(gen, inst);
#line 497 "./jit-rules-arm.sel"
		{
			arm_test_reg_reg(inst, ARM_CMP, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg2].cpu_reg);
			arm_alu_reg_imm8_cond(inst, ARM_MOV, _jit_reg_info[reg].cpu_reg, 0, 1, ARM_CC_LT);
			arm_alu_reg_imm8_cond(inst, ARM_MOV, _jit_reg_info[reg].cpu_reg, 0, 0, ARM_CC_GE);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

case JIT_OP_ILT_UN:
{
	arm_inst_buf inst;
	int reg;
	int reg2;
	jit_nint imm_value;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	if(insn->value2->is_nint_constant && insn->value2->address >= 0 && insn->value2->address <= 255)
	{
		imm_value = insn->value2->address;
		jit_gen_load_inst_ptr(gen, inst);
#line 504 "./jit-rules-arm.sel"
		{
			arm_test_reg_imm8(inst, ARM_CMP, _jit_reg_info[reg].cpu_reg, imm_value);
			arm_alu_reg_imm8_cond(inst, ARM_MOV, _jit_reg_info[reg].cpu_reg, 0, 1, ARM_CC_LT_UN);
			arm_alu_reg_imm8_cond(inst, ARM_MOV, _jit_reg_info[reg].cpu_reg, 0, 0, ARM_CC_GE_UN);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	else
	{
		reg2 = _jit_regs_load_value(gen, insn->value2, 0, (insn->flags & (JIT_INSN_VALUE2_NEXT_USE | JIT_INSN_VALUE2_LIVE)));
		jit_gen_load_inst_ptr(gen, inst);
#line 509 "./jit-rules-arm.sel"
		{
			arm_test_reg_reg(inst, ARM_CMP, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg2].cpu_reg);
			arm_alu_reg_imm8_cond(inst, ARM_MOV, _jit_reg_info[reg].cpu_reg, 0, 1, ARM_CC_LT_UN);
			arm_alu_reg_imm8_cond(inst, ARM_MOV, _jit_reg_info[reg].cpu_reg, 0, 0, ARM_CC_GE_UN);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

case JIT_OP_ILE:
{
	arm_inst_buf inst;
	int reg;
	int reg2;
	jit_nint imm_value;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	if(insn->value2->is_nint_constant && insn->value2->address >= 0 && insn->value2->address <= 255)
	{
		imm_value = insn->value2->address;
		jit_gen_load_inst_ptr(gen, inst);
#line 516 "./jit-rules-arm.sel"
		{
			arm_test_reg_imm8(inst, ARM_CMP, _jit_reg_info[reg].cpu_reg, imm_value);
			arm_alu_reg_imm8_cond(inst, ARM_MOV, _jit_reg_info[reg].cpu_reg, 0, 1, ARM_CC_LE);
			arm_alu_reg_imm8_cond(inst, ARM_MOV, _jit_reg_info[reg].cpu_reg, 0, 0, ARM_CC_GT);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	else
	{
		reg2 = _jit_regs_load_value(gen, insn->value2, 0, (insn->flags & (JIT_INSN_VALUE2_NEXT_USE | JIT_INSN_VALUE2_LIVE)));
		jit_gen_load_inst_ptr(gen, inst);
#line 521 "./jit-rules-arm.sel"
		{
			arm_test_reg_reg(inst, ARM_CMP, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg2].cpu_reg);
			arm_alu_reg_imm8_cond(inst, ARM_MOV, _jit_reg_info[reg].cpu_reg, 0, 1, ARM_CC_LE);
			arm_alu_reg_imm8_cond(inst, ARM_MOV, _jit_reg_info[reg].cpu_reg, 0, 0, ARM_CC_GT);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

case JIT_OP_ILE_UN:
{
	arm_inst_buf inst;
	int reg;
	int reg2;
	jit_nint imm_value;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	if(insn->value2->is_nint_constant && insn->value2->address >= 0 && insn->value2->address <= 255)
	{
		imm_value = insn->value2->address;
		jit_gen_load_inst_ptr(gen, inst);
#line 528 "./jit-rules-arm.sel"
		{
			arm_test_reg_imm8(inst, ARM_CMP, _jit_reg_info[reg].cpu_reg, imm_value);
			arm_alu_reg_imm8_cond(inst, ARM_MOV, _jit_reg_info[reg].cpu_reg, 0, 1, ARM_CC_LE_UN);
			arm_alu_reg_imm8_cond(inst, ARM_MOV, _jit_reg_info[reg].cpu_reg, 0, 0, ARM_CC_GT_UN);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	else
	{
		reg2 = _jit_regs_load_value(gen, insn->value2, 0, (insn->flags & (JIT_INSN_VALUE2_NEXT_USE | JIT_INSN_VALUE2_LIVE)));
		jit_gen_load_inst_ptr(gen, inst);
#line 533 "./jit-rules-arm.sel"
		{
			arm_test_reg_reg(inst, ARM_CMP, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg2].cpu_reg);
			arm_alu_reg_imm8_cond(inst, ARM_MOV, _jit_reg_info[reg].cpu_reg, 0, 1, ARM_CC_LE_UN);
			arm_alu_reg_imm8_cond(inst, ARM_MOV, _jit_reg_info[reg].cpu_reg, 0, 0, ARM_CC_GT_UN);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

case JIT_OP_IGT:
{
	arm_inst_buf inst;
	int reg;
	int reg2;
	jit_nint imm_value;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	if(insn->value2->is_nint_constant && insn->value2->address >= 0 && insn->value2->address <= 255)
	{
		imm_value = insn->value2->address;
		jit_gen_load_inst_ptr(gen, inst);
#line 540 "./jit-rules-arm.sel"
		{
			arm_test_reg_imm8(inst, ARM_CMP, _jit_reg_info[reg].cpu_reg, imm_value);
			arm_alu_reg_imm8_cond(inst, ARM_MOV, _jit_reg_info[reg].cpu_reg, 0, 1, ARM_CC_GT);
			arm_alu_reg_imm8_cond(inst, ARM_MOV, _jit_reg_info[reg].cpu_reg, 0, 0, ARM_CC_LE);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	else
	{
		reg2 = _jit_regs_load_value(gen, insn->value2, 0, (insn->flags & (JIT_INSN_VALUE2_NEXT_USE | JIT_INSN_VALUE2_LIVE)));
		jit_gen_load_inst_ptr(gen, inst);
#line 545 "./jit-rules-arm.sel"
		{
			arm_test_reg_reg(inst, ARM_CMP, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg2].cpu_reg);
			arm_alu_reg_imm8_cond(inst, ARM_MOV, _jit_reg_info[reg].cpu_reg, 0, 1, ARM_CC_GT);
			arm_alu_reg_imm8_cond(inst, ARM_MOV, _jit_reg_info[reg].cpu_reg, 0, 0, ARM_CC_LE);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

case JIT_OP_IGT_UN:
{
	arm_inst_buf inst;
	int reg;
	int reg2;
	jit_nint imm_value;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	if(insn->value2->is_nint_constant && insn->value2->address >= 0 && insn->value2->address <= 255)
	{
		imm_value = insn->value2->address;
		jit_gen_load_inst_ptr(gen, inst);
#line 552 "./jit-rules-arm.sel"
		{
			arm_test_reg_imm8(inst, ARM_CMP, _jit_reg_info[reg].cpu_reg, imm_value);
			arm_alu_reg_imm8_cond(inst, ARM_MOV, _jit_reg_info[reg].cpu_reg, 0, 1, ARM_CC_GT_UN);
			arm_alu_reg_imm8_cond(inst, ARM_MOV, _jit_reg_info[reg].cpu_reg, 0, 0, ARM_CC_LE_UN);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	else
	{
		reg2 = _jit_regs_load_value(gen, insn->value2, 0, (insn->flags & (JIT_INSN_VALUE2_NEXT_USE | JIT_INSN_VALUE2_LIVE)));
		jit_gen_load_inst_ptr(gen, inst);
#line 557 "./jit-rules-arm.sel"
		{
			arm_test_reg_reg(inst, ARM_CMP, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg2].cpu_reg);
			arm_alu_reg_imm8_cond(inst, ARM_MOV, _jit_reg_info[reg].cpu_reg, 0, 1, ARM_CC_GT_UN);
			arm_alu_reg_imm8_cond(inst, ARM_MOV, _jit_reg_info[reg].cpu_reg, 0, 0, ARM_CC_LE_UN);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

case JIT_OP_IGE:
{
	arm_inst_buf inst;
	int reg;
	int reg2;
	jit_nint imm_value;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	if(insn->value2->is_nint_constant && insn->value2->address >= 0 && insn->value2->address <= 255)
	{
		imm_value = insn->value2->address;
		jit_gen_load_inst_ptr(gen, inst);
#line 564 "./jit-rules-arm.sel"
		{
			arm_test_reg_imm8(inst, ARM_CMP, _jit_reg_info[reg].cpu_reg, imm_value);
			arm_alu_reg_imm8_cond(inst, ARM_MOV, _jit_reg_info[reg].cpu_reg, 0, 1, ARM_CC_GE);
			arm_alu_reg_imm8_cond(inst, ARM_MOV, _jit_reg_info[reg].cpu_reg, 0, 0, ARM_CC_LT);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	else
	{
		reg2 = _jit_regs_load_value(gen, insn->value2, 0, (insn->flags & (JIT_INSN_VALUE2_NEXT_USE | JIT_INSN_VALUE2_LIVE)));
		jit_gen_load_inst_ptr(gen, inst);
#line 569 "./jit-rules-arm.sel"
		{
			arm_test_reg_reg(inst, ARM_CMP, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg2].cpu_reg);
			arm_alu_reg_imm8_cond(inst, ARM_MOV, _jit_reg_info[reg].cpu_reg, 0, 1, ARM_CC_GE);
			arm_alu_reg_imm8_cond(inst, ARM_MOV, _jit_reg_info[reg].cpu_reg, 0, 0, ARM_CC_LT);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

case JIT_OP_IGE_UN:
{
	arm_inst_buf inst;
	int reg;
	int reg2;
	jit_nint imm_value;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	if(insn->value2->is_nint_constant && insn->value2->address >= 0 && insn->value2->address <= 255)
	{
		imm_value = insn->value2->address;
		jit_gen_load_inst_ptr(gen, inst);
#line 576 "./jit-rules-arm.sel"
		{
			arm_test_reg_imm8(inst, ARM_CMP, _jit_reg_info[reg].cpu_reg, imm_value);
			arm_alu_reg_imm8_cond(inst, ARM_MOV, _jit_reg_info[reg].cpu_reg, 0, 1, ARM_CC_GE_UN);
			arm_alu_reg_imm8_cond(inst, ARM_MOV, _jit_reg_info[reg].cpu_reg, 0, 0, ARM_CC_LT_UN);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	else
	{
		reg2 = _jit_regs_load_value(gen, insn->value2, 0, (insn->flags & (JIT_INSN_VALUE2_NEXT_USE | JIT_INSN_VALUE2_LIVE)));
		jit_gen_load_inst_ptr(gen, inst);
#line 581 "./jit-rules-arm.sel"
		{
			arm_test_reg_reg(inst, ARM_CMP, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg2].cpu_reg);
			arm_alu_reg_imm8_cond(inst, ARM_MOV, _jit_reg_info[reg].cpu_reg, 0, 1, ARM_CC_GE_UN);
			arm_alu_reg_imm8_cond(inst, ARM_MOV, _jit_reg_info[reg].cpu_reg, 0, 0, ARM_CC_LT_UN);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

case JIT_OP_CHECK_NULL:
{
	arm_inst_buf inst;
	int reg;
	reg = _jit_regs_load_value(gen, insn->value1, 0, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	{
		jit_gen_load_inst_ptr(gen, inst);
#line 592 "./jit-rules-arm.sel"
		{
			arm_test_reg_imm8(inst, ARM_CMP, _jit_reg_info[reg].cpu_reg, 0);
			throw_builtin(&inst, func, ARM_CC_EQ, JIT_RESULT_NULL_REFERENCE);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
}
break;

case JIT_OP_CALL:
{
	arm_inst_buf inst;
	{
		jit_gen_load_inst_ptr(gen, inst);
#line 602 "./jit-rules-arm.sel"
		{
			jit_function_t func = (jit_function_t)(insn->dest);
			arm_call(inst, func->closure_entry);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
}
break;

case JIT_OP_CALL_TAIL:
{
	arm_inst_buf inst;
	{
		jit_gen_load_inst_ptr(gen, inst);
#line 608 "./jit-rules-arm.sel"
		{
			jit_function_t func = (jit_function_t)(insn->dest);
			arm_pop_frame_tail(inst, 0);
			arm_jump(inst, func->closure_entry);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
}
break;

case JIT_OP_CALL_INDIRECT:
{
	arm_inst_buf inst;
	{
		jit_gen_load_inst_ptr(gen, inst);
#line 615 "./jit-rules-arm.sel"
		{
			arm_mov_reg_reg((inst), ARM_LINK, ARM_PC);
			arm_mov_reg_reg((inst), ARM_PC, ARM_WORK);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
}
break;

case JIT_OP_CALL_VTABLE_PTR:
{
	arm_inst_buf inst;
	{
		jit_gen_load_inst_ptr(gen, inst);
#line 621 "./jit-rules-arm.sel"
		{
			arm_mov_reg_reg((inst), ARM_LINK, ARM_PC);
			arm_mov_reg_reg((inst), ARM_PC, ARM_WORK);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
}
break;

case JIT_OP_CALL_EXTERNAL:
{
	arm_inst_buf inst;
	{
		jit_gen_load_inst_ptr(gen, inst);
#line 627 "./jit-rules-arm.sel"
		{
			arm_call(inst, (void *)(insn->dest));
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
}
break;

case JIT_OP_RETURN:
{
	arm_inst_buf inst;
	{
		jit_gen_load_inst_ptr(gen, inst);
#line 632 "./jit-rules-arm.sel"
		{
			jump_to_epilog(gen, &inst, block);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
}
break;

case JIT_OP_RETURN_INT:
{
	arm_inst_buf inst;
	int reg;
	reg = _jit_regs_load_value(gen, insn->value1, 0, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	{
		_jit_regs_spill_all(gen);
		jit_gen_load_inst_ptr(gen, inst);
#line 637 "./jit-rules-arm.sel"
		{
			int cpu_reg = _jit_reg_info[reg].cpu_reg;
			if(cpu_reg != ARM_R0)
			{
				arm_mov_reg_reg(inst, ARM_R0, cpu_reg);
			}
			jump_to_epilog(gen, &inst, block);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
}
break;

case JIT_OP_RETURN_LONG:
{
	arm_inst_buf inst;
	int reg;
	jit_nint imm_value;
	jit_nint local_offset;
	if(insn->value1->is_constant)
	{
		imm_value = insn->value1->address;
		_jit_regs_spill_all(gen);
		jit_gen_load_inst_ptr(gen, inst);
#line 647 "./jit-rules-arm.sel"
		{
			mov_reg_imm(gen, &inst, ARM_R0, ((jit_int *)(imm_value))[0]);
			mov_reg_imm(gen, &inst, ARM_R1, ((jit_int *)(imm_value))[1]);
			jump_to_epilog(gen, &inst, block);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	else if(insn->value1->in_frame && !(insn->value1->in_register))
	{
		local_offset = insn->value1->frame_offset;
		_jit_regs_spill_all(gen);
		jit_gen_load_inst_ptr(gen, inst);
#line 652 "./jit-rules-arm.sel"
		{
			arm_load_membase(inst, ARM_R0, ARM_FP, local_offset);
			arm_load_membase(inst, ARM_R1, ARM_FP, local_offset + 4);
			jump_to_epilog(gen, &inst, block);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	else
	{
		reg = _jit_regs_load_value(gen, insn->value1, 0, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
		_jit_regs_spill_all(gen);
		jit_gen_load_inst_ptr(gen, inst);
#line 657 "./jit-rules-arm.sel"
		{
			if(_jit_reg_info[reg].cpu_reg != 0)
			{
				arm_mov_reg_reg(inst, ARM_R0, _jit_reg_info[reg].cpu_reg);
				arm_mov_reg_reg(inst, ARM_R1, _jit_reg_info[_jit_reg_info[reg].other_reg].cpu_reg);
			}
			jump_to_epilog(gen, &inst, block);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
}
break;

#ifdef JIT_ARM_HAS_FLOAT_REGS

case JIT_OP_RETURN_FLOAT32:
{
	arm_inst_buf inst;
	int reg;
	reg = _jit_regs_load_value(gen, insn->value1, 0, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	{
		_jit_regs_spill_all(gen);
		jit_gen_load_inst_ptr(gen, inst);
#line 667 "./jit-rules-arm.sel"
		{
			if(_jit_reg_info[reg].cpu_reg != 0)
			{
				arm_alu_freg_32(inst, ARM_MVF, ARM_F0, _jit_reg_info[reg].cpu_reg);
			}
			jump_to_epilog(gen, &inst, block);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
}
break;

#endif /* JIT_ARM_HAS_FLOAT_REGS */

#ifndef JIT_ARM_HAS_FLOAT_REGS

case JIT_OP_RETURN_FLOAT32:
{
#line 676 "./jit-rules-arm.sel"
		{
			arm_inst_buf inst;
			_jit_regs_spill_all(gen);
			_jit_gen_fix_value(insn->value1);
			jit_gen_load_inst_ptr(gen, inst);
			if(insn->value1->is_constant)
			{
				mov_reg_imm
					(gen, &inst, ARM_R0, ((int *)(insn->value1->address))[0]);
			}
			else
			{
				arm_load_membase(inst, ARM_R0, ARM_FP, insn->value1->frame_offset);
			}
			jump_to_epilog(gen, &inst, block);
			jit_gen_save_inst_ptr(gen, inst);
		}
}
break;

#endif /* !JIT_ARM_HAS_FLOAT_REGS */

#ifdef JIT_ARM_HAS_FLOAT_REGS

case JIT_OP_RETURN_FLOAT64:
case JIT_OP_RETURN_NFLOAT:
{
	arm_inst_buf inst;
	int reg;
	reg = _jit_regs_load_value(gen, insn->value1, 0, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	{
		_jit_regs_spill_all(gen);
		jit_gen_load_inst_ptr(gen, inst);
#line 696 "./jit-rules-arm.sel"
		{
			if(_jit_reg_info[reg].cpu_reg != 0)
			{
				arm_alu_freg(inst, ARM_MVF, ARM_F0, _jit_reg_info[reg].cpu_reg);
			}
			jump_to_epilog(gen, &inst, block);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
}
break;

#endif /* JIT_ARM_HAS_FLOAT_REGS */

#ifndef JIT_ARM_HAS_FLOAT_REGS

case JIT_OP_RETURN_FLOAT64:
case JIT_OP_RETURN_NFLOAT:
{
#line 705 "./jit-rules-arm.sel"
		{
			arm_inst_buf inst;
			_jit_regs_spill_all(gen);
			_jit_gen_fix_value(insn->value1);
			jit_gen_load_inst_ptr(gen, inst);
			if(insn->value1->is_constant)
			{
				mov_reg_imm
					(gen, &inst, ARM_R0, ((int *)(insn->value1->address))[0]);
				mov_reg_imm
					(gen, &inst, ARM_R1, ((int *)(insn->value1->address))[1]);
			}
			else
			{
				arm_load_membase(inst, ARM_R0, ARM_FP, insn->value1->frame_offset);
				arm_load_membase(inst, ARM_R1, ARM_FP,
								 insn->value1->frame_offset + 4);
			}
			jump_to_epilog(gen, &inst, block);
			jit_gen_save_inst_ptr(gen, inst);
		}
}
break;

#endif /* !JIT_ARM_HAS_FLOAT_REGS */

case JIT_OP_RETURN_SMALL_STRUCT:
{
	arm_inst_buf inst;
	int reg;
	reg = _jit_regs_load_value(gen, insn->value1, 0, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	{
		_jit_regs_spill_all(gen);
		jit_gen_load_inst_ptr(gen, inst);
#line 728 "./jit-rules-arm.sel"
		{
			int temp_reg = _jit_reg_info[reg].cpu_reg;
			if(temp_reg < 3)
			{
				arm_mov_reg_reg(inst, ARM_WORK, temp_reg);
				temp_reg = ARM_WORK;
			}
			switch(insn->value2->address)
			{
				case 1:
				{
					arm_load_membase_byte(inst, ARM_R0, temp_reg, 0);
				}
				break;
	
				case 2:
				{
					arm_load_membase_ushort(inst, ARM_R0, temp_reg, 0);
				}
				break;
	
				case 3:
				{
					arm_load_membase_ushort(inst, ARM_R0, temp_reg, 0);
					arm_load_membase_byte(inst, ARM_R1, temp_reg, 2);
					arm_shift_reg_imm8(inst, ARM_SHL, ARM_R1, ARM_R1, 16);
					arm_alu_reg_reg(inst, ARM_ORR, ARM_R0, ARM_R0, ARM_R1);
				}
				break;
	
				case 4:
				{
					arm_load_membase(inst, ARM_R0, temp_reg, 0);
				}
				break;
	
				case 5:
				{
					arm_load_membase(inst, ARM_R0, temp_reg, 0);
					arm_load_membase_byte(inst, ARM_R1, temp_reg, 4);
				}
				break;
	
				case 6:
				{
					arm_load_membase(inst, ARM_R0, temp_reg, 0);
					arm_load_membase_ushort(inst, ARM_R1, temp_reg, 4);
				}
				break;
	
				case 7:
				{
					arm_load_membase(inst, ARM_R0, temp_reg, 0);
					arm_load_membase_ushort(inst, ARM_R1, temp_reg, 4);
					arm_load_membase_byte(inst, ARM_R2, temp_reg, 6);
					arm_shift_reg_imm8(inst, ARM_SHL, ARM_R2, ARM_R2, 16);
					arm_alu_reg_reg(inst, ARM_ORR, ARM_R1, ARM_R1, ARM_R2);
				}
				break;
	
				case 8:
				{
					arm_load_membase(inst, ARM_R0, temp_reg, 0);
					arm_load_membase(inst, ARM_R1, temp_reg, 4);
				}
				break;
			}
			jump_to_epilog(gen, &inst, block);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
}
break;

case JIT_OP_SETUP_FOR_NESTED:
{
	arm_inst_buf inst;
	_jit_regs_spill_all(gen);
	{
		jit_gen_load_inst_ptr(gen, inst);
#line 799 "./jit-rules-arm.sel"
		{
			jit_nint nest_reg = jit_value_get_nint_constant(insn->value1);
			if(nest_reg == -1)
			{
				arm_push_reg(inst, ARM_FP);
			}
			else
			{
				arm_mov_reg_reg(inst, _jit_reg_info[nest_reg].cpu_reg, ARM_FP);
			}
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
}
break;

case JIT_OP_SETUP_FOR_SIBLING:
{
	arm_inst_buf inst;
	_jit_regs_spill_all(gen);
	{
		jit_gen_load_inst_ptr(gen, inst);
#line 812 "./jit-rules-arm.sel"
		{
			jit_nint level = jit_value_get_nint_constant(insn->value1);
			jit_nint nest_reg = jit_value_get_nint_constant(insn->value2);
			int cpu_reg;
			if(nest_reg == -1)
			{
				cpu_reg = ARM_R0;
			}
			else
			{
				cpu_reg = _jit_reg_info[nest_reg].cpu_reg;
			}
			arm_load_membase(inst, cpu_reg, ARM_FP, JIT_APPLY_PARENT_FRAME_OFFSET);
			while(level > 0)
			{
				arm_load_membase(inst, cpu_reg, cpu_reg,
								 JIT_APPLY_PARENT_FRAME_OFFSET);
				--level;
			}
			if(nest_reg == -1)
			{
				arm_push_reg(inst, cpu_reg);
			}
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
}
break;

case JIT_OP_IMPORT:
{
	arm_inst_buf inst;
	{
		jit_gen_load_inst_ptr(gen, inst);
#line 838 "./jit-rules-arm.sel"
		{
			/* TODO */
			TODO();
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
}
break;

case JIT_OP_COPY_LOAD_SBYTE:
{
	arm_inst_buf inst;
	int reg;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	{
		jit_gen_load_inst_ptr(gen, inst);
#line 848 "./jit-rules-arm.sel"
		{}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

case JIT_OP_COPY_LOAD_UBYTE:
{
	arm_inst_buf inst;
	int reg;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	{
		jit_gen_load_inst_ptr(gen, inst);
#line 851 "./jit-rules-arm.sel"
		{}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

case JIT_OP_COPY_LOAD_SHORT:
{
	arm_inst_buf inst;
	int reg;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	{
		jit_gen_load_inst_ptr(gen, inst);
#line 854 "./jit-rules-arm.sel"
		{}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

case JIT_OP_COPY_LOAD_USHORT:
{
	arm_inst_buf inst;
	int reg;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	{
		jit_gen_load_inst_ptr(gen, inst);
#line 857 "./jit-rules-arm.sel"
		{}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

case JIT_OP_COPY_INT:
{
	arm_inst_buf inst;
	int reg;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	{
		jit_gen_load_inst_ptr(gen, inst);
#line 860 "./jit-rules-arm.sel"
		{}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

case JIT_OP_COPY_LONG:
{
	arm_inst_buf inst;
	int reg;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	{
		jit_gen_load_inst_ptr(gen, inst);
#line 863 "./jit-rules-arm.sel"
		{}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

#ifdef JIT_ARM_HAS_FLOAT_REGS

case JIT_OP_COPY_FLOAT32:
{
	arm_inst_buf inst;
	int reg;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	{
		jit_gen_load_inst_ptr(gen, inst);
#line 866 "./jit-rules-arm.sel"
		{}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

#endif /* JIT_ARM_HAS_FLOAT_REGS */

#ifndef JIT_ARM_HAS_FLOAT_REGS

case JIT_OP_COPY_FLOAT32:
{
#line 869 "./jit-rules-arm.sel"
		{
			arm_inst_buf inst;
			_jit_regs_force_out(gen, insn->value1, 0);
			_jit_regs_force_out(gen, insn->dest, 1);
			_jit_gen_fix_value(insn->value1);
			_jit_gen_fix_value(insn->dest);
			jit_gen_load_inst_ptr(gen, inst);
			if(insn->value1->is_constant)
			{
				mov_reg_imm
					(gen, &inst, ARM_WORK, ((int *)(insn->value1->address))[0]);
			}
			else
			{
				arm_load_membase(inst, ARM_WORK, ARM_FP,
								 insn->value1->frame_offset);
			}
			arm_store_membase(inst, ARM_WORK, ARM_FP, insn->dest->frame_offset);
			jit_gen_save_inst_ptr(gen, inst);
		}
}
break;

#endif /* !JIT_ARM_HAS_FLOAT_REGS */

#ifdef JIT_ARM_HAS_FLOAT_REGS

case JIT_OP_COPY_FLOAT64:
case JIT_OP_COPY_NFLOAT:
{
	arm_inst_buf inst;
	int reg;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	{
		jit_gen_load_inst_ptr(gen, inst);
#line 891 "./jit-rules-arm.sel"
		{}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

#endif /* JIT_ARM_HAS_FLOAT_REGS */

#ifndef JIT_ARM_HAS_FLOAT_REGS

case JIT_OP_COPY_FLOAT64:
case JIT_OP_COPY_NFLOAT:
{
#line 894 "./jit-rules-arm.sel"
		{
			arm_inst_buf inst;
			_jit_regs_force_out(gen, insn->value1, 0);
			_jit_regs_force_out(gen, insn->dest, 1);
			_jit_gen_fix_value(insn->value1);
			_jit_gen_fix_value(insn->dest);
			jit_gen_load_inst_ptr(gen, inst);
			if(insn->value1->is_constant)
			{
				mov_reg_imm
					(gen, &inst, ARM_WORK, ((int *)(insn->value1->address))[0]);
				arm_store_membase(inst, ARM_WORK, ARM_FP,
								  insn->dest->frame_offset);
				mov_reg_imm
					(gen, &inst, ARM_WORK, ((int *)(insn->value1->address))[1]);
				arm_store_membase(inst, ARM_WORK, ARM_FP,
								  insn->dest->frame_offset + 4);
			}
			else
			{
				arm_load_membase(inst, ARM_WORK, ARM_FP,
								 insn->value1->frame_offset);
				arm_store_membase(inst, ARM_WORK, ARM_FP,
								  insn->dest->frame_offset);
				arm_load_membase(inst, ARM_WORK, ARM_FP,
								 insn->value1->frame_offset + 4);
				arm_store_membase(inst, ARM_WORK, ARM_FP,
								  insn->dest->frame_offset + 4);
			}
			jit_gen_save_inst_ptr(gen, inst);
		}
}
break;

#endif /* !JIT_ARM_HAS_FLOAT_REGS */

case JIT_OP_COPY_STRUCT:
{
#line 927 "./jit-rules-arm.sel"
		{
			/* TODO */
			TODO();
		}
}
break;

case JIT_OP_COPY_STORE_BYTE:
{
#line 933 "./jit-rules-arm.sel"
		{
			arm_inst_buf inst;
			int reg;
			_jit_regs_force_out(gen, insn->dest, 1);
			_jit_gen_fix_value(insn->dest);
			reg = _jit_regs_load_value
				(gen, insn->value1, 0,
				 (insn->flags & (JIT_INSN_VALUE1_NEXT_USE |
				 				 JIT_INSN_VALUE1_LIVE)));
			jit_gen_load_inst_ptr(gen, inst);
			arm_store_membase_byte(inst, _jit_reg_info[reg].cpu_reg,
								   ARM_FP, insn->dest->frame_offset);
			jit_gen_save_inst_ptr(gen, inst);
		}
}
break;

case JIT_OP_COPY_STORE_SHORT:
{
#line 949 "./jit-rules-arm.sel"
		{
			arm_inst_buf inst;
			int reg;
			_jit_regs_force_out(gen, insn->dest, 1);
			_jit_gen_fix_value(insn->dest);
			reg = _jit_regs_load_value
				(gen, insn->value1, 1,
				 (insn->flags & (JIT_INSN_VALUE1_NEXT_USE |
				 				 JIT_INSN_VALUE1_LIVE)));
			jit_gen_load_inst_ptr(gen, inst);
			arm_store_membase_short(inst, _jit_reg_info[reg].cpu_reg,
								    ARM_FP, insn->dest->frame_offset);
			jit_gen_save_inst_ptr(gen, inst);
			_jit_regs_free_reg(gen, reg, 1);
		}
}
break;

case JIT_OP_ADDRESS_OF:
{
#line 966 "./jit-rules-arm.sel"
		{
			arm_inst_buf inst;
			int reg, offset;
			_jit_regs_force_out(gen, insn->value1, 0);
			_jit_gen_fix_value(insn->value1);
			jit_gen_load_inst_ptr(gen, inst);
			reg = _jit_regs_dest_value(gen, insn->dest);
			reg = _jit_reg_info[reg].cpu_reg;
			offset = insn->value1->frame_offset;
			if(offset > 0)
			{
				arm_alu_reg_imm(inst, ARM_ADD, reg, ARM_FP, offset);
			}
			else if(offset < 0)
			{
				arm_alu_reg_imm(inst, ARM_SUB, reg, ARM_FP, -offset);
			}
			else
			{
				arm_mov_reg_reg(inst, reg, ARM_FP);
			}
			jit_gen_save_inst_ptr(gen, inst);
		}
}
break;

case JIT_OP_RETURN_REG:
{
#line 995 "./jit-rules-arm.sel"
		{ /* Nothing to do here */ }
}
break;

case JIT_OP_PUSH_INT:
{
	arm_inst_buf inst;
	int reg;
	reg = _jit_regs_load_value(gen, insn->value1, 0, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	{
		jit_gen_load_inst_ptr(gen, inst);
#line 998 "./jit-rules-arm.sel"
		{
			arm_push_reg(inst, _jit_reg_info[reg].cpu_reg);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
}
break;

case JIT_OP_PUSH_LONG:
{
	arm_inst_buf inst;
	int reg;
	reg = _jit_regs_load_value(gen, insn->value1, 0, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	{
		jit_gen_load_inst_ptr(gen, inst);
#line 1003 "./jit-rules-arm.sel"
		{
			arm_push_reg(inst, _jit_reg_info[_jit_reg_info[reg].other_reg].cpu_reg);
			arm_push_reg(inst, _jit_reg_info[reg].cpu_reg);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
}
break;

#ifdef JIT_ARM_HAS_FLOAT_REGS

case JIT_OP_PUSH_FLOAT32:
{
	arm_inst_buf inst;
	int reg;
	reg = _jit_regs_load_value(gen, insn->value1, 0, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	{
		jit_gen_load_inst_ptr(gen, inst);
#line 1009 "./jit-rules-arm.sel"
		{
			arm_push_reg_float32(inst, _jit_reg_info[reg].cpu_reg);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
}
break;

#endif /* JIT_ARM_HAS_FLOAT_REGS */

#ifndef JIT_ARM_HAS_FLOAT_REGS

case JIT_OP_PUSH_FLOAT32:
{
#line 1014 "./jit-rules-arm.sel"
		{
			arm_inst_buf inst;
			_jit_regs_force_out(gen, insn->value1, 0);
			_jit_gen_fix_value(insn->value1);
			jit_gen_load_inst_ptr(gen, inst);
			if(insn->value1->is_constant)
			{
				mov_reg_imm
					(gen, &inst, ARM_WORK, ((int *)(insn->value1->address))[0]);
			}
			else
			{
				arm_load_membase(inst, ARM_WORK, ARM_FP,
								 insn->value1->frame_offset);
			}
			arm_push_reg(inst, ARM_WORK);
			jit_gen_save_inst_ptr(gen, inst);
		}
}
break;

#endif /* !JIT_ARM_HAS_FLOAT_REGS */

#ifdef JIT_ARM_HAS_FLOAT_REGS

case JIT_OP_PUSH_FLOAT64:
case JIT_OP_PUSH_NFLOAT:
{
	arm_inst_buf inst;
	int reg;
	reg = _jit_regs_load_value(gen, insn->value1, 0, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	{
		jit_gen_load_inst_ptr(gen, inst);
#line 1034 "./jit-rules-arm.sel"
		{
			arm_push_reg_float64(inst, _jit_reg_info[reg].cpu_reg);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
}
break;

#endif /* JIT_ARM_HAS_FLOAT_REGS */

#ifndef JIT_ARM_HAS_FLOAT_REGS

case JIT_OP_PUSH_FLOAT64:
case JIT_OP_PUSH_NFLOAT:
{
#line 1039 "./jit-rules-arm.sel"
		{
			arm_inst_buf inst;
			_jit_regs_force_out(gen, insn->value1, 0);
			_jit_gen_fix_value(insn->value1);
			jit_gen_load_inst_ptr(gen, inst);
			if(insn->value1->is_constant)
			{
				mov_reg_imm
					(gen, &inst, ARM_WORK, ((int *)(insn->value1->address))[1]);
				arm_push_reg(inst, ARM_WORK);
				mov_reg_imm
					(gen, &inst, ARM_WORK, ((int *)(insn->value1->address))[0]);
				arm_push_reg(inst, ARM_WORK);
			}
			else
			{
				arm_load_membase(inst, ARM_WORK, ARM_FP,
								 insn->value1->frame_offset + 4);
				arm_push_reg(inst, ARM_WORK);
				arm_load_membase(inst, ARM_WORK, ARM_FP,
								 insn->value1->frame_offset);
				arm_push_reg(inst, ARM_WORK);
			}
			jit_gen_save_inst_ptr(gen, inst);
		}
}
break;

#endif /* !JIT_ARM_HAS_FLOAT_REGS */

case JIT_OP_PUSH_STRUCT:
{
	arm_inst_buf inst;
	int reg;
	reg = _jit_regs_load_value(gen, insn->value1, 0, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	{
		jit_gen_load_inst_ptr(gen, inst);
#line 1066 "./jit-rules-arm.sel"
		{
			/* TODO */
			TODO();
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
}
break;

case JIT_OP_POP_STACK:
{
	arm_inst_buf inst;
	{
		jit_gen_load_inst_ptr(gen, inst);
#line 1072 "./jit-rules-arm.sel"
		{
			arm_alu_reg_imm(inst, ARM_ADD, ARM_SP, ARM_SP, insn->value1->address);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
}
break;

case JIT_OP_FLUSH_SMALL_STRUCT:
{
	arm_inst_buf inst;
	{
		jit_gen_load_inst_ptr(gen, inst);
#line 1077 "./jit-rules-arm.sel"
		{
			jit_nuint size;
			jit_nint offset;
			_jit_gen_fix_value(insn->value1);
			size = jit_type_get_size(jit_value_get_type(insn->value1));
			offset = insn->value1->frame_offset;
			switch(size)
			{
				case 1:
				{
					arm_store_membase_byte(inst, ARM_R0, ARM_FP, offset);
				}
				break;
	
				case 2:
				{
					arm_store_membase_short(inst, ARM_R0, ARM_FP, offset);
				}
				break;
	
				case 3:
				{
					arm_mov_reg_reg(inst, ARM_R1, ARM_R0);
					arm_store_membase_short(inst, ARM_R0, ARM_FP, offset);
					arm_shift_reg_imm8(inst, ARM_SHR, ARM_R0, ARM_R1, 16);
					arm_store_membase_byte(inst, ARM_R0, ARM_FP, offset + 2);
				}
				break;
	
				case 4:
				{
					arm_store_membase(inst, ARM_R0, ARM_FP, offset);
				}
				break;
	
				case 5:
				{
					arm_store_membase(inst, ARM_R0, ARM_FP, offset);
					arm_store_membase_byte(inst, ARM_R1, ARM_FP, offset + 4);
				}
				break;
	
				case 6:
				{
					arm_store_membase(inst, ARM_R0, ARM_FP, offset);
					arm_store_membase_short(inst, ARM_R1, ARM_FP, offset + 4);
				}
				break;
	
				case 7:
				{
					arm_store_membase(inst, ARM_R0, ARM_FP, offset);
					arm_mov_reg_reg(inst, ARM_R2, ARM_R1);
					arm_store_membase_short(inst, ARM_R1, ARM_FP, offset + 4);
					arm_shift_reg_imm8(inst, ARM_SHR, ARM_R1, ARM_R2, 16);
					arm_store_membase_byte(inst, ARM_R1, ARM_FP, offset + 6);
				}
				break;
	
				case 8:
				{
					arm_store_membase(inst, ARM_R0, ARM_FP, offset);
					arm_store_membase(inst, ARM_R1, ARM_FP, offset + 4);
				}
				break;
			}
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
}
break;

case JIT_OP_SET_PARAM_INT:
{
	arm_inst_buf inst;
	int reg;
	reg = _jit_regs_load_value(gen, insn->value1, 0, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	{
		jit_gen_load_inst_ptr(gen, inst);
#line 1146 "./jit-rules-arm.sel"
		{
			arm_store_membase(inst, _jit_reg_info[reg].cpu_reg, ARM_SP, insn->value2->address);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
}
break;

case JIT_OP_SET_PARAM_LONG:
{
	arm_inst_buf inst;
	int reg;
	reg = _jit_regs_load_value(gen, insn->value1, 0, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	{
		jit_gen_load_inst_ptr(gen, inst);
#line 1151 "./jit-rules-arm.sel"
		{
			arm_store_membase(inst, _jit_reg_info[reg].cpu_reg, ARM_SP, insn->value2->address);
			arm_store_membase(inst, _jit_reg_info[_jit_reg_info[reg].other_reg].cpu_reg, ARM_SP, insn->value2->address + 4);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
}
break;

#ifdef JIT_ARM_HAS_FLOAT_REGS

case JIT_OP_SET_PARAM_FLOAT32:
{
	arm_inst_buf inst;
	int reg;
	reg = _jit_regs_load_value(gen, insn->value1, 0, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	{
		jit_gen_load_inst_ptr(gen, inst);
#line 1157 "./jit-rules-arm.sel"
		{
			arm_store_membase_float32(inst, _jit_reg_info[reg].cpu_reg, ARM_SP, insn->value2->address);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
}
break;

#endif /* JIT_ARM_HAS_FLOAT_REGS */

#ifndef JIT_ARM_HAS_FLOAT_REGS

case JIT_OP_SET_PARAM_FLOAT32:
{
#line 1162 "./jit-rules-arm.sel"
		{
			arm_inst_buf inst;
			_jit_regs_force_out(gen, insn->value1, 0);
			_jit_gen_fix_value(insn->value1);
			jit_gen_load_inst_ptr(gen, inst);
			if(insn->value1->is_constant)
			{
				mov_reg_imm
					(gen, &inst, ARM_WORK, ((int *)(insn->value1->address))[0]);
				arm_store_membase
					(inst, ARM_WORK, ARM_SP, insn->value2->address);
			}
			else
			{
				arm_load_membase(inst, ARM_WORK, ARM_FP,
								 insn->value1->frame_offset);
				arm_store_membase
					(inst, ARM_WORK, ARM_SP, insn->value2->address);
			}
			jit_gen_save_inst_ptr(gen, inst);
		}
}
break;

#endif /* !JIT_ARM_HAS_FLOAT_REGS */

#ifdef JIT_ARM_HAS_FLOAT_REGS

case JIT_OP_SET_PARAM_FLOAT64:
case JIT_OP_SET_PARAM_NFLOAT:
{
	arm_inst_buf inst;
	int reg;
	reg = _jit_regs_load_value(gen, insn->value1, 0, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	{
		jit_gen_load_inst_ptr(gen, inst);
#line 1186 "./jit-rules-arm.sel"
		{
			arm_store_membase_float64(inst, _jit_reg_info[reg].cpu_reg, ARM_SP, insn->value2->address);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
}
break;

#endif /* JIT_ARM_HAS_FLOAT_REGS */

#ifndef JIT_ARM_HAS_FLOAT_REGS

case JIT_OP_SET_PARAM_FLOAT64:
case JIT_OP_SET_PARAM_NFLOAT:
{
#line 1192 "./jit-rules-arm.sel"
		{
			arm_inst_buf inst;
			_jit_regs_force_out(gen, insn->value1, 0);
			_jit_gen_fix_value(insn->value1);
			jit_gen_load_inst_ptr(gen, inst);
			if(insn->value1->is_constant)
			{
				mov_reg_imm
					(gen, &inst, ARM_WORK, ((int *)(insn->value1->address))[0]);
				arm_store_membase
					(inst, ARM_WORK, ARM_SP, insn->value2->address);
				mov_reg_imm
					(gen, &inst, ARM_WORK, ((int *)(insn->value1->address))[1]);
				arm_store_membase
					(inst, ARM_WORK, ARM_SP, insn->value2->address + 4);
			}
			else
			{
				arm_load_membase(inst, ARM_WORK, ARM_FP,
								 insn->value1->frame_offset);
				arm_store_membase
					(inst, ARM_WORK, ARM_SP, insn->value2->address);
				arm_load_membase(inst, ARM_WORK, ARM_FP,
								 insn->value1->frame_offset + 4);
				arm_store_membase
					(inst, ARM_WORK, ARM_SP, insn->value2->address + 4);
			}
			jit_gen_save_inst_ptr(gen, inst);
		}
}
break;

#endif /* !JIT_ARM_HAS_FLOAT_REGS */

case JIT_OP_SET_PARAM_STRUCT:
{
	arm_inst_buf inst;
	int reg;
	reg = _jit_regs_load_value(gen, insn->value1, 0, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	{
		jit_gen_load_inst_ptr(gen, inst);
#line 1223 "./jit-rules-arm.sel"
		{
			/* TODO */
			TODO();
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
}
break;

case JIT_OP_LOAD_RELATIVE_SBYTE:
{
	arm_inst_buf inst;
	int reg;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	{
		jit_gen_load_inst_ptr(gen, inst);
#line 1233 "./jit-rules-arm.sel"
		{
			arm_load_membase_sbyte(inst, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, insn->value2->address);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

case JIT_OP_LOAD_RELATIVE_UBYTE:
{
	arm_inst_buf inst;
	int reg;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	{
		jit_gen_load_inst_ptr(gen, inst);
#line 1238 "./jit-rules-arm.sel"
		{
			arm_load_membase_byte(inst, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, insn->value2->address);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

case JIT_OP_LOAD_RELATIVE_SHORT:
{
	arm_inst_buf inst;
	int reg;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	{
		jit_gen_load_inst_ptr(gen, inst);
#line 1243 "./jit-rules-arm.sel"
		{
			arm_load_membase_short(inst, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, insn->value2->address);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

case JIT_OP_LOAD_RELATIVE_USHORT:
{
	arm_inst_buf inst;
	int reg;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	{
		jit_gen_load_inst_ptr(gen, inst);
#line 1248 "./jit-rules-arm.sel"
		{
			arm_load_membase_ushort(inst, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, insn->value2->address);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

case JIT_OP_LOAD_RELATIVE_INT:
{
	arm_inst_buf inst;
	int reg;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	{
		jit_gen_load_inst_ptr(gen, inst);
#line 1253 "./jit-rules-arm.sel"
		{
			arm_load_membase(inst, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, insn->value2->address);
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

case JIT_OP_LOAD_RELATIVE_LONG:
{
#line 1258 "./jit-rules-arm.sel"
		{
			arm_inst_buf inst;
			int reg = _jit_regs_load_value
				(gen, insn->value1, 0,
				 (insn->flags & (JIT_INSN_VALUE1_NEXT_USE |
				 				 JIT_INSN_VALUE1_LIVE)));
			int reg2, reg3;
			int frame_offset;
			_jit_gen_fix_value(insn->dest);
			_jit_regs_get_reg_pair(gen, reg, -1, -1, &reg2, &reg3);
			reg  = _jit_reg_info[reg].cpu_reg;
			reg2 = _jit_reg_info[reg2].cpu_reg;
			reg3 = _jit_reg_info[reg3].cpu_reg;
			frame_offset = insn->dest->frame_offset;
			jit_gen_load_inst_ptr(gen, inst);
			arm_load_membase(inst, reg2, reg, insn->value2->address);
			arm_load_membase(inst, reg3, reg, insn->value2->address + 4);
			arm_store_membase(inst, reg2, ARM_FP, frame_offset);
			arm_store_membase(inst, reg3, ARM_FP, frame_offset + 4);
			insn->dest->in_frame = 1;
			jit_gen_save_inst_ptr(gen, inst);
		}
}
break;

case JIT_OP_LOAD_RELATIVE_FLOAT32:
{
#line 1282 "./jit-rules-arm.sel"
		{
			/* TODO */
			TODO();
		}
}
break;

case JIT_OP_LOAD_RELATIVE_FLOAT64:
case JIT_OP_LOAD_RELATIVE_NFLOAT:
{
#line 1288 "./jit-rules-arm.sel"
		{
			/* TODO */
			TODO();
		}
}
break;

case JIT_OP_LOAD_RELATIVE_STRUCT:
{
#line 1294 "./jit-rules-arm.sel"
		{
			/* TODO */
			TODO();
		}
}
break;

case JIT_OP_STORE_RELATIVE_BYTE:
{
#line 1300 "./jit-rules-arm.sel"
		{
			arm_inst_buf inst;
			int reg = _jit_regs_load_value
				(gen, insn->dest, 0,
				 (insn->flags & (JIT_INSN_DEST_NEXT_USE |
				 				 JIT_INSN_DEST_LIVE)));
			int reg2 = _jit_regs_load_value
				(gen, insn->value1, 0,
				 (insn->flags & (JIT_INSN_VALUE1_NEXT_USE |
				 				 JIT_INSN_VALUE1_LIVE)));
			jit_gen_load_inst_ptr(gen, inst);
			reg  = _jit_reg_info[reg].cpu_reg;
			reg2 = _jit_reg_info[reg2].cpu_reg;
			arm_store_membase_byte(inst, reg2, reg, insn->value2->address);
			jit_gen_save_inst_ptr(gen, inst);
		}
}
break;

case JIT_OP_STORE_RELATIVE_SHORT:
{
#line 1318 "./jit-rules-arm.sel"
		{
			arm_inst_buf inst;
			int reg = _jit_regs_load_value
				(gen, insn->dest, 0,
				 (insn->flags & (JIT_INSN_DEST_NEXT_USE |
				 				 JIT_INSN_DEST_LIVE)));
			int reg2 = _jit_regs_load_value
				(gen, insn->value1, 1,
				 (insn->flags & (JIT_INSN_VALUE1_NEXT_USE |
				 				 JIT_INSN_VALUE1_LIVE)));
			jit_gen_load_inst_ptr(gen, inst);
			reg  = _jit_reg_info[reg].cpu_reg;
			reg2 = _jit_reg_info[reg2].cpu_reg;
			arm_store_membase_short(inst, reg2, reg, insn->value2->address);
			jit_gen_save_inst_ptr(gen, inst);
			_jit_regs_free_reg(gen, reg2, 1);
		}
}
break;

case JIT_OP_STORE_RELATIVE_INT:
{
#line 1337 "./jit-rules-arm.sel"
		{
			arm_inst_buf inst;
			int reg = _jit_regs_load_value
				(gen, insn->dest, 0,
				 (insn->flags & (JIT_INSN_DEST_NEXT_USE |
				 				 JIT_INSN_DEST_LIVE)));
			int reg2 = _jit_regs_load_value
				(gen, insn->value1, 0,
				 (insn->flags & (JIT_INSN_VALUE1_NEXT_USE |
				 				 JIT_INSN_VALUE1_LIVE)));
			jit_gen_load_inst_ptr(gen, inst);
			reg  = _jit_reg_info[reg].cpu_reg;
			reg2 = _jit_reg_info[reg2].cpu_reg;
			arm_store_membase(inst, reg2, reg, insn->value2->address);
			jit_gen_save_inst_ptr(gen, inst);
		}
}
break;

case JIT_OP_STORE_RELATIVE_LONG:
{
#line 1355 "./jit-rules-arm.sel"
		{
			arm_inst_buf inst;
			int reg = _jit_regs_load_value
				(gen, insn->dest, 0,
				 (insn->flags & (JIT_INSN_DEST_NEXT_USE |
				 				 JIT_INSN_DEST_LIVE)));
			int reg2, reg3;
			int frame_offset;
			_jit_regs_get_reg_pair(gen, reg, -1, -1, &reg2, &reg3);
			_jit_gen_fix_value(insn->value1);
			jit_gen_load_inst_ptr(gen, inst);
			reg  = _jit_reg_info[reg].cpu_reg;
			reg2 = _jit_reg_info[reg2].cpu_reg;
			reg3 = _jit_reg_info[reg3].cpu_reg;
			frame_offset = insn->value1->frame_offset;
			arm_load_membase(inst, reg2, ARM_FP, frame_offset);
			arm_load_membase(inst, reg3, ARM_FP, frame_offset + 4);
			arm_store_membase(inst, reg2, reg, insn->value2->address);
			arm_store_membase(inst, reg3, reg, insn->value2->address + 4);
			jit_gen_save_inst_ptr(gen, inst);
		}
}
break;

case JIT_OP_STORE_RELATIVE_FLOAT32:
{
#line 1378 "./jit-rules-arm.sel"
		{
			/* TODO */
			TODO();
		}
}
break;

case JIT_OP_STORE_RELATIVE_FLOAT64:
case JIT_OP_STORE_RELATIVE_NFLOAT:
{
#line 1384 "./jit-rules-arm.sel"
		{
			/* TODO */
			TODO();
		}
}
break;

case JIT_OP_STORE_RELATIVE_STRUCT:
{
#line 1390 "./jit-rules-arm.sel"
		{
			/* TODO */
			TODO();
		}
}
break;

case JIT_OP_ADD_RELATIVE:
{
	arm_inst_buf inst;
	int reg;
	reg = _jit_regs_load_value(gen, insn->value1, 1, (insn->flags & (JIT_INSN_VALUE1_NEXT_USE | JIT_INSN_VALUE1_LIVE)));
	{
		jit_gen_load_inst_ptr(gen, inst);
#line 1396 "./jit-rules-arm.sel"
		{
			if(insn->value2->address != 0)
			{
				arm_alu_reg_imm(inst, ARM_ADD, _jit_reg_info[reg].cpu_reg, _jit_reg_info[reg].cpu_reg, insn->value2->address);
			}
		}
		jit_gen_save_inst_ptr(gen, inst);
	}
	if((insn->flags & JIT_INSN_DEST_NEXT_USE) != 0)
	{
		_jit_regs_set_value(gen, reg, insn->dest, 0);
	}
	else
	{
		int other_reg;
		if(gen->contents[reg].is_long_start)
		{
			other_reg = _jit_reg_info[reg].other_reg;
		}
		else
		{
			other_reg = -1;
		}
		_jit_gen_spill_reg(gen, reg, other_reg, insn->dest);
		if(insn->dest->has_global_register)
			insn->dest->in_global_register = 1;
		else
			insn->dest->in_frame = 1;
		_jit_regs_free_reg(gen, reg, 1);
	}
}
break;

#elif defined(JIT_INCLUDE_SUPPORTED)

case JIT_OP_TRUNC_SBYTE:
case JIT_OP_TRUNC_UBYTE:
case JIT_OP_TRUNC_SHORT:
case JIT_OP_TRUNC_USHORT:
case JIT_OP_IADD:
case JIT_OP_ISUB:
case JIT_OP_IMUL:
case JIT_OP_INEG:
case JIT_OP_LADD:
case JIT_OP_LSUB:
case JIT_OP_LNEG:
#ifdef JIT_ARM_HAS_FLOAT_REGS
case JIT_OP_FADD:
#endif
#ifdef JIT_ARM_HAS_FLOAT_REGS
case JIT_OP_FSUB:
#endif
#ifdef JIT_ARM_HAS_FLOAT_REGS
case JIT_OP_FMUL:
#endif
#ifdef JIT_ARM_HAS_FLOAT_REGS
case JIT_OP_FDIV:
#endif
#ifdef JIT_ARM_HAS_FLOAT_REGS
case JIT_OP_FNEG:
#endif
#ifdef JIT_ARM_HAS_FLOAT_REGS
case JIT_OP_DADD:
case JIT_OP_NFADD:
#endif
#ifdef JIT_ARM_HAS_FLOAT_REGS
case JIT_OP_DSUB:
case JIT_OP_NFSUB:
#endif
#ifdef JIT_ARM_HAS_FLOAT_REGS
case JIT_OP_DMUL:
case JIT_OP_NFMUL:
#endif
#ifdef JIT_ARM_HAS_FLOAT_REGS
case JIT_OP_DDIV:
case JIT_OP_NFDIV:
#endif
#ifdef JIT_ARM_HAS_FLOAT_REGS
case JIT_OP_DNEG:
case JIT_OP_NFNEG:
#endif
case JIT_OP_IAND:
case JIT_OP_IOR:
case JIT_OP_IXOR:
case JIT_OP_INOT:
case JIT_OP_ISHL:
case JIT_OP_ISHR:
case JIT_OP_ISHR_UN:
case JIT_OP_LAND:
case JIT_OP_LOR:
case JIT_OP_LXOR:
case JIT_OP_LNOT:
case JIT_OP_BR:
case JIT_OP_BR_IFALSE:
case JIT_OP_BR_ITRUE:
case JIT_OP_BR_IEQ:
case JIT_OP_BR_INE:
case JIT_OP_BR_ILT:
case JIT_OP_BR_ILT_UN:
case JIT_OP_BR_ILE:
case JIT_OP_BR_ILE_UN:
case JIT_OP_BR_IGT:
case JIT_OP_BR_IGT_UN:
case JIT_OP_BR_IGE:
case JIT_OP_BR_IGE_UN:
case JIT_OP_ICMP:
case JIT_OP_ICMP_UN:
case JIT_OP_IEQ:
case JIT_OP_INE:
case JIT_OP_ILT:
case JIT_OP_ILT_UN:
case JIT_OP_ILE:
case JIT_OP_ILE_UN:
case JIT_OP_IGT:
case JIT_OP_IGT_UN:
case JIT_OP_IGE:
case JIT_OP_IGE_UN:
case JIT_OP_CHECK_NULL:
case JIT_OP_CALL:
case JIT_OP_CALL_TAIL:
case JIT_OP_CALL_INDIRECT:
case JIT_OP_CALL_VTABLE_PTR:
case JIT_OP_CALL_EXTERNAL:
case JIT_OP_RETURN:
case JIT_OP_RETURN_INT:
case JIT_OP_RETURN_LONG:
#ifdef JIT_ARM_HAS_FLOAT_REGS
case JIT_OP_RETURN_FLOAT32:
#endif
#ifndef JIT_ARM_HAS_FLOAT_REGS
case JIT_OP_RETURN_FLOAT32:
#endif
#ifdef JIT_ARM_HAS_FLOAT_REGS
case JIT_OP_RETURN_FLOAT64:
case JIT_OP_RETURN_NFLOAT:
#endif
#ifndef JIT_ARM_HAS_FLOAT_REGS
case JIT_OP_RETURN_FLOAT64:
case JIT_OP_RETURN_NFLOAT:
#endif
case JIT_OP_RETURN_SMALL_STRUCT:
case JIT_OP_SETUP_FOR_NESTED:
case JIT_OP_SETUP_FOR_SIBLING:
case JIT_OP_IMPORT:
case JIT_OP_COPY_LOAD_SBYTE:
case JIT_OP_COPY_LOAD_UBYTE:
case JIT_OP_COPY_LOAD_SHORT:
case JIT_OP_COPY_LOAD_USHORT:
case JIT_OP_COPY_INT:
case JIT_OP_COPY_LONG:
#ifdef JIT_ARM_HAS_FLOAT_REGS
case JIT_OP_COPY_FLOAT32:
#endif
#ifndef JIT_ARM_HAS_FLOAT_REGS
case JIT_OP_COPY_FLOAT32:
#endif
#ifdef JIT_ARM_HAS_FLOAT_REGS
case JIT_OP_COPY_FLOAT64:
case JIT_OP_COPY_NFLOAT:
#endif
#ifndef JIT_ARM_HAS_FLOAT_REGS
case JIT_OP_COPY_FLOAT64:
case JIT_OP_COPY_NFLOAT:
#endif
case JIT_OP_COPY_STRUCT:
case JIT_OP_COPY_STORE_BYTE:
case JIT_OP_COPY_STORE_SHORT:
case JIT_OP_ADDRESS_OF:
case JIT_OP_RETURN_REG:
case JIT_OP_PUSH_INT:
case JIT_OP_PUSH_LONG:
#ifdef JIT_ARM_HAS_FLOAT_REGS
case JIT_OP_PUSH_FLOAT32:
#endif
#ifndef JIT_ARM_HAS_FLOAT_REGS
case JIT_OP_PUSH_FLOAT32:
#endif
#ifdef JIT_ARM_HAS_FLOAT_REGS
case JIT_OP_PUSH_FLOAT64:
case JIT_OP_PUSH_NFLOAT:
#endif
#ifndef JIT_ARM_HAS_FLOAT_REGS
case JIT_OP_PUSH_FLOAT64:
case JIT_OP_PUSH_NFLOAT:
#endif
case JIT_OP_PUSH_STRUCT:
case JIT_OP_POP_STACK:
case JIT_OP_FLUSH_SMALL_STRUCT:
case JIT_OP_SET_PARAM_INT:
case JIT_OP_SET_PARAM_LONG:
#ifdef JIT_ARM_HAS_FLOAT_REGS
case JIT_OP_SET_PARAM_FLOAT32:
#endif
#ifndef JIT_ARM_HAS_FLOAT_REGS
case JIT_OP_SET_PARAM_FLOAT32:
#endif
#ifdef JIT_ARM_HAS_FLOAT_REGS
case JIT_OP_SET_PARAM_FLOAT64:
case JIT_OP_SET_PARAM_NFLOAT:
#endif
#ifndef JIT_ARM_HAS_FLOAT_REGS
case JIT_OP_SET_PARAM_FLOAT64:
case JIT_OP_SET_PARAM_NFLOAT:
#endif
case JIT_OP_SET_PARAM_STRUCT:
case JIT_OP_LOAD_RELATIVE_SBYTE:
case JIT_OP_LOAD_RELATIVE_UBYTE:
case JIT_OP_LOAD_RELATIVE_SHORT:
case JIT_OP_LOAD_RELATIVE_USHORT:
case JIT_OP_LOAD_RELATIVE_INT:
case JIT_OP_LOAD_RELATIVE_LONG:
case JIT_OP_LOAD_RELATIVE_FLOAT32:
case JIT_OP_LOAD_RELATIVE_FLOAT64:
case JIT_OP_LOAD_RELATIVE_NFLOAT:
case JIT_OP_LOAD_RELATIVE_STRUCT:
case JIT_OP_STORE_RELATIVE_BYTE:
case JIT_OP_STORE_RELATIVE_SHORT:
case JIT_OP_STORE_RELATIVE_INT:
case JIT_OP_STORE_RELATIVE_LONG:
case JIT_OP_STORE_RELATIVE_FLOAT32:
case JIT_OP_STORE_RELATIVE_FLOAT64:
case JIT_OP_STORE_RELATIVE_NFLOAT:
case JIT_OP_STORE_RELATIVE_STRUCT:
case JIT_OP_ADD_RELATIVE:
	return 1;

#endif