/* loads.s: DO NOT EDIT! Automatically generated by makeloads */
 opcode (0x41)
op41:
 movb %cl,%ch
 dispatch
 opcode (0x42)
op42:
 movb %dh,%ch
 dispatch
 opcode (0x43)
op43:
 movb %dl,%ch
 dispatch
 opcode (0x44)
op44:
 movb %bh,%ch
 dispatch
 opcode (0x45)
op45:
 movb %bl,%ch
 dispatch
 opcode (0x46)
op46:
 movb (%ebx,%ebp),%ch
 dispatch
 opcode (0x46)
ix46:
 GETIXOFF
 movb (%edi,%ebp),%ch
 dispatch
 opcode (0x46)
iy46:
 GETIYOFF
 movb (%edi,%ebp),%ch
 dispatch
 opcode (0x47)
op47:
 movb %al,%ch
 dispatch
 opcode (0x48)
op48:
 movb %ch,%cl
 dispatch
 opcode (0x4a)
op4a:
 movb %dh,%cl
 dispatch
 opcode (0x4b)
op4b:
 movb %dl,%cl
 dispatch
 opcode (0x4c)
op4c:
 movb %bh,%cl
 dispatch
 opcode (0x4d)
op4d:
 movb %bl,%cl
 dispatch
 opcode (0x4e)
op4e:
 movb (%ebx,%ebp),%cl
 dispatch
 opcode (0x4e)
ix4e:
 GETIXOFF
 movb (%edi,%ebp),%cl
 dispatch
 opcode (0x4e)
iy4e:
 GETIYOFF
 movb (%edi,%ebp),%cl
 dispatch
 opcode (0x4f)
op4f:
 movb %al,%cl
 dispatch
 opcode (0x50)
op50:
 movb %ch,%dh
 dispatch
 opcode (0x51)
op51:
 movb %cl,%dh
 dispatch
 opcode (0x53)
op53:
 movb %dl,%dh
 dispatch
 opcode (0x54)
op54:
 movb %bh,%dh
 dispatch
 opcode (0x55)
op55:
 movb %bl,%dh
 dispatch
 opcode (0x56)
op56:
 movb (%ebx,%ebp),%dh
 dispatch
 opcode (0x56)
ix56:
 GETIXOFF
 movb (%edi,%ebp),%dh
 dispatch
 opcode (0x56)
iy56:
 GETIYOFF
 movb (%edi,%ebp),%dh
 dispatch
 opcode (0x57)
op57:
 movb %al,%dh
 dispatch
 opcode (0x58)
op58:
 movb %ch,%dl
 dispatch
 opcode (0x59)
op59:
 movb %cl,%dl
 dispatch
 opcode (0x5a)
op5a:
 movb %dh,%dl
 dispatch
 opcode (0x5c)
op5c:
 movb %bh,%dl
 dispatch
 opcode (0x5d)
op5d:
 movb %bl,%dl
 dispatch
 opcode (0x5e)
op5e:
 movb (%ebx,%ebp),%dl
 dispatch
 opcode (0x5e)
ix5e:
 GETIXOFF
 movb (%edi,%ebp),%dl
 dispatch
 opcode (0x5e)
iy5e:
 GETIYOFF
 movb (%edi,%ebp),%dl
 dispatch
 opcode (0x5f)
op5f:
 movb %al,%dl
 dispatch
 opcode (0x60)
op60:
 movb %ch,%bh
 dispatch
 opcode (0x61)
op61:
 movb %cl,%bh
 dispatch
 opcode (0x62)
op62:
 movb %dh,%bh
 dispatch
 opcode (0x63)
op63:
 movb %dl,%bh
 dispatch
 opcode (0x65)
op65:
 movb %bl,%bh
 dispatch
 opcode (0x66)
op66:
 movb (%ebx,%ebp),%bh
 dispatch
 opcode (0x66)
ix66:
 GETIXOFF
 movb (%edi,%ebp),%bh
 dispatch
 opcode (0x66)
iy66:
 GETIYOFF
 movb (%edi,%ebp),%bh
 dispatch
 opcode (0x67)
op67:
 movb %al,%bh
 dispatch
 opcode (0x68)
op68:
 movb %ch,%bl
 dispatch
 opcode (0x69)
op69:
 movb %cl,%bl
 dispatch
 opcode (0x6a)
op6a:
 movb %dh,%bl
 dispatch
 opcode (0x6b)
op6b:
 movb %dl,%bl
 dispatch
 opcode (0x6c)
op6c:
 movb %bh,%bl
 dispatch
 opcode (0x6e)
op6e:
 movb (%ebx,%ebp),%bl
 dispatch
 opcode (0x6e)
ix6e:
 GETIXOFF
 movb (%edi,%ebp),%bl
 dispatch
 opcode (0x6e)
iy6e:
 GETIYOFF
 movb (%edi,%ebp),%bl
 dispatch
 opcode (0x6f)
op6f:
 movb %al,%bl
 dispatch
 opcode (0x70)
op70:
 movb %ch,(%ebx,%ebp)
 dispatch
 opcode (0x70)
ix70:
 GETIXOFF
 movb %ch,(%edi,%ebp)
 dispatch
 opcode (0x70)
iy70:
 GETIYOFF
 movb %ch,(%edi,%ebp)
 dispatch
 opcode (0x71)
op71:
 movb %cl,(%ebx,%ebp)
 dispatch
 opcode (0x71)
ix71:
 GETIXOFF
 movb %cl,(%edi,%ebp)
 dispatch
 opcode (0x71)
iy71:
 GETIYOFF
 movb %cl,(%edi,%ebp)
 dispatch
 opcode (0x72)
op72:
 movb %dh,(%ebx,%ebp)
 dispatch
 opcode (0x72)
ix72:
 GETIXOFF
 movb %dh,(%edi,%ebp)
 dispatch
 opcode (0x72)
iy72:
 GETIYOFF
 movb %dh,(%edi,%ebp)
 dispatch
 opcode (0x73)
op73:
 movb %dl,(%ebx,%ebp)
 dispatch
 opcode (0x73)
ix73:
 GETIXOFF
 movb %dl,(%edi,%ebp)
 dispatch
 opcode (0x73)
iy73:
 GETIYOFF
 movb %dl,(%edi,%ebp)
 dispatch
 opcode (0x74)
op74:
 movb %bh,(%ebx,%ebp)
 dispatch
 opcode (0x74)
ix74:
 GETIXOFF
 movb %bh,(%edi,%ebp)
 dispatch
 opcode (0x74)
iy74:
 GETIYOFF
 movb %bh,(%edi,%ebp)
 dispatch
 opcode (0x75)
op75:
 movb %bl,(%ebx,%ebp)
 dispatch
 opcode (0x75)
ix75:
 GETIXOFF
 movb %bl,(%edi,%ebp)
 dispatch
 opcode (0x75)
iy75:
 GETIYOFF
 movb %bl,(%edi,%ebp)
 dispatch
 opcode (0x77)
op77:
 movb %al,(%ebx,%ebp)
 dispatch
 opcode (0x77)
ix77:
 GETIXOFF
 movb %al,(%edi,%ebp)
 dispatch
 opcode (0x77)
iy77:
 GETIYOFF
 movb %al,(%edi,%ebp)
 dispatch
 opcode (0x78)
op78:
 movb %ch,%al
 dispatch
 opcode (0x79)
op79:
 movb %cl,%al
 dispatch
 opcode (0x7a)
op7a:
 movb %dh,%al
 dispatch
 opcode (0x7b)
op7b:
 movb %dl,%al
 dispatch
 opcode (0x7c)
op7c:
 movb %bh,%al
 dispatch
 opcode (0x7d)
op7d:
 movb %bl,%al
 dispatch
 opcode (0x7e)
op7e:
 movb (%ebx,%ebp),%al
 dispatch
 opcode (0x7e)
ix7e:
 GETIXOFF
 movb (%edi,%ebp),%al
 dispatch
 opcode (0x7e)
iy7e:
 GETIYOFF
 movb (%edi,%ebp),%al
 dispatch
 opcode (0x80)
op80:
 andb $0xd5,%ah	/* ADD A,reg */
 addb %ch,%al
 jmp setaddadc
 opcode (0x81)
op81:
 andb $0xd5,%ah	/* ADD A,reg */
 addb %cl,%al
 jmp setaddadc
 opcode (0x82)
op82:
 andb $0xd5,%ah	/* ADD A,reg */
 addb %dh,%al
 jmp setaddadc
 opcode (0x83)
op83:
 andb $0xd5,%ah	/* ADD A,reg */
 addb %dl,%al
 jmp setaddadc
 opcode (0x84)
op84:
 andb $0xd5,%ah	/* ADD A,reg */
 addb %bh,%al
 jmp setaddadc
 opcode (0x85)
op85:
 andb $0xd5,%ah	/* ADD A,reg */
 addb %bl,%al
 jmp setaddadc
 opcode (0x86)
op86:
 andb $0xd5,%ah	/* ADD A,reg */
 addb (%ebx,%ebp),%al
 jmp setaddadc
 opcode (0x87)
op87:
 andb $0xd5,%ah	/* ADD A,reg */
 addb %al,%al
 jmp setaddadc
 opcode (0x88)
ix86:
 GETIXOFF
 andb $0xd5,%ah	/* ADD A,reg */
 addb (%edi,%ebp),%al
 jmp setaddadc
 opcode (0x89)
iy86:
 GETIYOFF
 andb $0xd5,%ah	/* ADD A,reg */
 addb (%edi,%ebp),%al
 jmp setaddadc
 opcode (0x88)
op88:
 andb $0xd5,%ah	/* ADC A,reg */
 sahf
 adcb %ch,%al
 jmp setaddadc
 opcode (0x89)
op89:
 andb $0xd5,%ah	/* ADC A,reg */
 sahf
 adcb %cl,%al
 jmp setaddadc
 opcode (0x8a)
op8a:
 andb $0xd5,%ah	/* ADC A,reg */
 sahf
 adcb %dh,%al
 jmp setaddadc
 opcode (0x8b)
op8b:
 andb $0xd5,%ah	/* ADC A,reg */
 sahf
 adcb %dl,%al
 jmp setaddadc
 opcode (0x8c)
op8c:
 andb $0xd5,%ah	/* ADC A,reg */
 sahf
 adcb %bh,%al
 jmp setaddadc
 opcode (0x8d)
op8d:
 andb $0xd5,%ah	/* ADC A,reg */
 sahf
 adcb %bl,%al
 jmp setaddadc
 opcode (0x8e)
op8e:
 andb $0xd5,%ah	/* ADC A,reg */
 sahf
 adcb (%ebx,%ebp),%al
 jmp setaddadc
 opcode (0x8f)
op8f:
 andb $0xd5,%ah	/* ADC A,reg */
 sahf
 adcb %al,%al
 jmp setaddadc
 opcode (0x90)
ix8e:
 GETIXOFF
 andb $0xd5,%ah	/* ADC A,reg */
 sahf
 adcb (%edi,%ebp),%al
 jmp setaddadc
 opcode (0x91)
iy8e:
 GETIYOFF
 andb $0xd5,%ah	/* ADC A,reg */
 sahf
 adcb (%edi,%ebp),%al
 jmp setaddadc
 opcode (0x90)
op90:
 orb $2,%ah	/* SUB reg */
 subb %ch,%al
 jmp setaddadc
 opcode (0x91)
op91:
 orb $2,%ah	/* SUB reg */
 subb %cl,%al
 jmp setaddadc
 opcode (0x92)
op92:
 orb $2,%ah	/* SUB reg */
 subb %dh,%al
 jmp setaddadc
 opcode (0x93)
op93:
 orb $2,%ah	/* SUB reg */
 subb %dl,%al
 jmp setaddadc
 opcode (0x94)
op94:
 orb $2,%ah	/* SUB reg */
 subb %bh,%al
 jmp setaddadc
 opcode (0x95)
op95:
 orb $2,%ah	/* SUB reg */
 subb %bl,%al
 jmp setaddadc
 opcode (0x96)
op96:
 orb $2,%ah	/* SUB reg */
 subb (%ebx,%ebp),%al
 jmp setaddadc
 opcode (0x97)
op97:
 orb $2,%ah	/* SUB reg */
 subb %al,%al
 jmp setaddadc
 opcode (0x98)
ix96:
 GETIXOFF
 orb $2,%ah	/* SUB reg */
 subb (%edi,%ebp),%al
 jmp setaddadc
 opcode (0x99)
iy96:
 GETIYOFF
 orb $2,%ah	/* SUB reg */
 subb (%edi,%ebp),%al
 jmp setaddadc
 opcode (0x98)
op98:
 orb $2,%ah	/* SBC A,reg */
 sahf
 sbbb %ch,%al
 jmp setaddadc
 opcode (0x99)
op99:
 orb $2,%ah	/* SBC A,reg */
 sahf
 sbbb %cl,%al
 jmp setaddadc
 opcode (0x9a)
op9a:
 orb $2,%ah	/* SBC A,reg */
 sahf
 sbbb %dh,%al
 jmp setaddadc
 opcode (0x9b)
op9b:
 orb $2,%ah	/* SBC A,reg */
 sahf
 sbbb %dl,%al
 jmp setaddadc
 opcode (0x9c)
op9c:
 orb $2,%ah	/* SBC A,reg */
 sahf
 sbbb %bh,%al
 jmp setaddadc
 opcode (0x9d)
op9d:
 orb $2,%ah	/* SBC A,reg */
 sahf
 sbbb %bl,%al
 jmp setaddadc
 opcode (0x9e)
op9e:
 orb $2,%ah	/* SBC A,reg */
 sahf
 sbbb (%ebx,%ebp),%al
 jmp setaddadc
 opcode (0x9f)
op9f:
 orb $2,%ah	/* SBC A,reg */
 sahf
 sbbb %al,%al
 jmp setaddadc
 opcode (0xa0)
ix9e:
 GETIXOFF
 orb $2,%ah	/* SBC A,reg */
 sahf
 sbbb (%edi,%ebp),%al
 jmp setaddadc
 opcode (0xa1)
iy9e:
 GETIYOFF
 orb $2,%ah	/* SBC A,reg */
 sahf
 sbbb (%edi,%ebp),%al
 jmp setaddadc
 opcode (0xa0)
opa0:
 andb %ch,%al	/* AND reg */
 lahf
 orb $0x10,%ah
 andb $0xd4,%ah
 dispatch
 opcode (0xa1)
opa1:
 andb %cl,%al	/* AND reg */
 lahf
 orb $0x10,%ah
 andb $0xd4,%ah
 dispatch
 opcode (0xa2)
opa2:
 andb %dh,%al	/* AND reg */
 lahf
 orb $0x10,%ah
 andb $0xd4,%ah
 dispatch
 opcode (0xa3)
opa3:
 andb %dl,%al	/* AND reg */
 lahf
 orb $0x10,%ah
 andb $0xd4,%ah
 dispatch
 opcode (0xa4)
opa4:
 andb %bh,%al	/* AND reg */
 lahf
 orb $0x10,%ah
 andb $0xd4,%ah
 dispatch
 opcode (0xa5)
opa5:
 andb %bl,%al	/* AND reg */
 lahf
 orb $0x10,%ah
 andb $0xd4,%ah
 dispatch
 opcode (0xa6)
opa6:
 andb (%ebx,%ebp),%al	/* AND reg */
 lahf
 orb $0x10,%ah
 andb $0xd4,%ah
 dispatch
 opcode (0xa7)
opa7:
 andb %al,%al	/* AND reg */
 lahf
 orb $0x10,%ah
 andb $0xd4,%ah
 dispatch
 opcode (0xa8)
ixa6:
 GETIXOFF
 andb (%edi,%ebp),%al	/* AND reg */
 lahf
 orb $0x10,%ah
 andb $0xd4,%ah
 dispatch
 opcode (0xa9)
iya6:
 GETIYOFF
 andb (%edi,%ebp),%al	/* AND reg */
 lahf
 orb $0x10,%ah
 andb $0xd4,%ah
 dispatch
 opcode (0xa8)
opa8:
 xorb %ch,%al	/* XOR reg */
 lahf
 andb $0xc4,%ah
 dispatch
 opcode (0xa9)
opa9:
 xorb %cl,%al	/* XOR reg */
 lahf
 andb $0xc4,%ah
 dispatch
 opcode (0xaa)
opaa:
 xorb %dh,%al	/* XOR reg */
 lahf
 andb $0xc4,%ah
 dispatch
 opcode (0xab)
opab:
 xorb %dl,%al	/* XOR reg */
 lahf
 andb $0xc4,%ah
 dispatch
 opcode (0xac)
opac:
 xorb %bh,%al	/* XOR reg */
 lahf
 andb $0xc4,%ah
 dispatch
 opcode (0xad)
opad:
 xorb %bl,%al	/* XOR reg */
 lahf
 andb $0xc4,%ah
 dispatch
 opcode (0xae)
opae:
 xorb (%ebx,%ebp),%al	/* XOR reg */
 lahf
 andb $0xc4,%ah
 dispatch
 opcode (0xaf)
opaf:
 xorb %al,%al	/* XOR reg */
 lahf
 andb $0xc4,%ah
 dispatch
 opcode (0xb0)
ixae:
 GETIXOFF
 xorb (%edi,%ebp),%al	/* XOR reg */
 lahf
 andb $0xc4,%ah
 dispatch
 opcode (0xb1)
iyae:
 GETIYOFF
 xorb (%edi,%ebp),%al	/* XOR reg */
 lahf
 andb $0xc4,%ah
 dispatch
 opcode (0xb0)
opb0:
 orb %ch,%al	/* OR reg */
 lahf
 andb $0xc4,%ah
 dispatch
 opcode (0xb1)
opb1:
 orb %cl,%al	/* OR reg */
 lahf
 andb $0xc4,%ah
 dispatch
 opcode (0xb2)
opb2:
 orb %dh,%al	/* OR reg */
 lahf
 andb $0xc4,%ah
 dispatch
 opcode (0xb3)
opb3:
 orb %dl,%al	/* OR reg */
 lahf
 andb $0xc4,%ah
 dispatch
 opcode (0xb4)
opb4:
 orb %bh,%al	/* OR reg */
 lahf
 andb $0xc4,%ah
 dispatch
 opcode (0xb5)
opb5:
 orb %bl,%al	/* OR reg */
 lahf
 andb $0xc4,%ah
 dispatch
 opcode (0xb6)
opb6:
 orb (%ebx,%ebp),%al	/* OR reg */
 lahf
 andb $0xc4,%ah
 dispatch
 opcode (0xb7)
opb7:
 orb %al,%al	/* OR reg */
 lahf
 andb $0xc4,%ah
 dispatch
 opcode (0xb8)
ixb6:
 GETIXOFF
 orb (%edi,%ebp),%al	/* OR reg */
 lahf
 andb $0xc4,%ah
 dispatch
 opcode (0xb9)
iyb6:
 GETIYOFF
 orb (%edi,%ebp),%al	/* OR reg */
 lahf
 andb $0xc4,%ah
 dispatch
 opcode (0xb8)
opb8:
 orb $2,%ah	/* CP reg */
 cmpb %ch,%al
 jmp setaddadc
 opcode (0xb9)
opb9:
 orb $2,%ah	/* CP reg */
 cmpb %cl,%al
 jmp setaddadc
 opcode (0xba)
opba:
 orb $2,%ah	/* CP reg */
 cmpb %dh,%al
 jmp setaddadc
 opcode (0xbb)
opbb:
 orb $2,%ah	/* CP reg */
 cmpb %dl,%al
 jmp setaddadc
 opcode (0xbc)
opbc:
 orb $2,%ah	/* CP reg */
 cmpb %bh,%al
 jmp setaddadc
 opcode (0xbd)
opbd:
 orb $2,%ah	/* CP reg */
 cmpb %bl,%al
 jmp setaddadc
 opcode (0xbe)
opbe:
 orb $2,%ah	/* CP reg */
 cmpb (%ebx,%ebp),%al
 jmp setaddadc
 opcode (0xbf)
opbf:
 orb $2,%ah	/* CP reg */
 cmpb %al,%al
 jmp setaddadc
 opcode (0xc0)
ixbe:
 GETIXOFF
 orb $2,%ah	/* CP reg */
 cmpb (%edi,%ebp),%al
 jmp setaddadc
 opcode (0xc1)
iybe:
 GETIYOFF
 orb $2,%ah	/* CP reg */
 cmpb (%edi,%ebp),%al
 jmp setaddadc
 opcode (0xcf)
opcf:
 movl $8,%edi	/* RST 08 */
 jmp docall_di
 opcode (0xd7)
opd7:
 movl $16,%edi	/* RST 10 */
 jmp docall_di
 opcode (0xdf)
opdf:
 movl $24,%edi	/* RST 18 */
 jmp docall_di
 opcode (0xe7)
ope7:
 movl $32,%edi	/* RST 20 */
 jmp docall_di
 opcode (0xef)
opef:
 movl $40,%edi	/* RST 28 */
 jmp docall_di
 opcode (0xf7)
opf7:
 movl $48,%edi	/* RST 30 */
 jmp docall_di
 opcode (0xff)
opff:
 movl $56,%edi	/* RST 38 */
 jmp docall_di
 opcode (0xc2)
opc2:
 sahf	/* JP NZ,nnnn */
 jnz opc3
 incl %esi
 incl %esi
 dispatch
 opcode (0xca)
opca:
 sahf	/* JP Z,nnnn */
 jz opc3
 incl %esi
 incl %esi
 dispatch
 opcode (0xd2)
opd2:
 sahf	/* JP NC,nnnn */
 jnc opc3
 incl %esi
 incl %esi
 dispatch
 opcode (0xda)
opda:
 sahf	/* JP C,nnnn */
 jc opc3
 incl %esi
 incl %esi
 dispatch
 opcode (0xe2)
ope2:
 sahf	/* JP PO,nnnn */
 jpo opc3
 incl %esi
 incl %esi
 dispatch
 opcode (0xea)
opea:
 sahf	/* JP PE,nnnn */
 jpe opc3
 incl %esi
 incl %esi
 dispatch
 opcode (0xf2)
opf2:
 sahf	/* JP P,nnnn */
 jns opc3
 incl %esi
 incl %esi
 dispatch
 opcode (0xfa)
opfa:
 sahf	/* JP M,nnnn */
 js opc3
 incl %esi
 incl %esi
 dispatch
 opcode (0xc0)
opc0:
 sahf	/* RET NZ */
 jnz opc9
 dispatch
 opcode (0xc8)
opc8:
 sahf	/* RET Z */
 jz opc9
 dispatch
 opcode (0xd0)
opd0:
 sahf	/* RET NC */
 jnc opc9
 dispatch
 opcode (0xd8)
opd8:
 sahf	/* RET C */
 jc opc9
 dispatch
 opcode (0xe0)
ope0:
 sahf	/* RET PO */
 jpo opc9
 dispatch
 opcode (0xe8)
ope8:
 sahf	/* RET PE */
 jpe opc9
 dispatch
 opcode (0xf0)
opf0:
 sahf	/* RET P */
 jns opc9
 dispatch
 opcode (0xf8)
opf8:
 sahf	/* RET M */
 js opc9
 dispatch
 opcode (0xc4)
opc4:
 sahf	/* CALL NZ,nnnn */
 jnz opcd
 incl %esi
 incl %esi
 dispatch
 opcode (0xcc)
opcc:
 sahf	/* CALL Z,nnnn */
 jz opcd
 incl %esi
 incl %esi
 dispatch
 opcode (0xd4)
opd4:
 sahf	/* CALL NC,nnnn */
 jnc opcd
 incl %esi
 incl %esi
 dispatch
 opcode (0xdc)
opdc:
 sahf	/* CALL C,nnnn */
 jc opcd
 incl %esi
 incl %esi
 dispatch
 opcode (0xe4)
ope4:
 sahf	/* CALL PO,nnnn */
 jpo opcd
 incl %esi
 incl %esi
 dispatch
 opcode (0xec)
opec:
 sahf	/* CALL PE,nnnn */
 jpe opcd
 incl %esi
 incl %esi
 dispatch
 opcode (0xf4)
opf4:
 sahf	/* CALL P,nnnn */
 jns opcd
 incl %esi
 incl %esi
 dispatch
 opcode (0xfc)
opfc:
 sahf	/* CALL M,nnnn */
 js opcd
 incl %esi
 incl %esi
 dispatch
 .align NALIGN,0x90
cb00: sahf
 rolb $1,%ch
 movzbl %ch,%edi
 jmp set_SZV
 .align NALIGN,0x90
cb01: sahf
 rolb $1,%cl
 movzbl %cl,%edi
 jmp set_SZV
 .align NALIGN,0x90
cb02: sahf
 rolb $1,%dh
 movzbl %dh,%edi
 jmp set_SZV
 .align NALIGN,0x90
cb03: sahf
 rolb $1,%dl
 movzbl %dl,%edi
 jmp set_SZV
 .align NALIGN,0x90
cb04: sahf
 rolb $1,%bh
 movzbl %bh,%edi
 jmp set_SZV
 .align NALIGN,0x90
cb05: sahf
 rolb $1,%bl
 movzbl %bl,%edi
 jmp set_SZV
 .align NALIGN,0x90
cb06: sahf
 rolb $1,(%edi,%ebp)
 movzbl (%edi,%ebp),%edi
 jmp set_SZV
 .align NALIGN,0x90
cb07: sahf
 rolb $1,%al
 movzbl %al,%edi
 jmp set_SZV
 .align NALIGN,0x90
cb08: sahf
 rorb $1,%ch
 movzbl %ch,%edi
 jmp set_SZV
 .align NALIGN,0x90
cb09: sahf
 rorb $1,%cl
 movzbl %cl,%edi
 jmp set_SZV
 .align NALIGN,0x90
cb0a: sahf
 rorb $1,%dh
 movzbl %dh,%edi
 jmp set_SZV
 .align NALIGN,0x90
cb0b: sahf
 rorb $1,%dl
 movzbl %dl,%edi
 jmp set_SZV
 .align NALIGN,0x90
cb0c: sahf
 rorb $1,%bh
 movzbl %bh,%edi
 jmp set_SZV
 .align NALIGN,0x90
cb0d: sahf
 rorb $1,%bl
 movzbl %bl,%edi
 jmp set_SZV
 .align NALIGN,0x90
cb0e: sahf
 rorb $1,(%edi,%ebp)
 movzbl (%edi,%ebp),%edi
 jmp set_SZV
 .align NALIGN,0x90
cb0f: sahf
 rorb $1,%al
 movzbl %al,%edi
 jmp set_SZV
 .align NALIGN,0x90
cb10: sahf
 rclb $1,%ch
 movzbl %ch,%edi
 jmp set_SZV
 .align NALIGN,0x90
cb11: sahf
 rclb $1,%cl
 movzbl %cl,%edi
 jmp set_SZV
 .align NALIGN,0x90
cb12: sahf
 rclb $1,%dh
 movzbl %dh,%edi
 jmp set_SZV
 .align NALIGN,0x90
cb13: sahf
 rclb $1,%dl
 movzbl %dl,%edi
 jmp set_SZV
 .align NALIGN,0x90
cb14: sahf
 rclb $1,%bh
 movzbl %bh,%edi
 jmp set_SZV
 .align NALIGN,0x90
cb15: sahf
 rclb $1,%bl
 movzbl %bl,%edi
 jmp set_SZV
 .align NALIGN,0x90
cb16: sahf
 rclb $1,(%edi,%ebp)
 movzbl (%edi,%ebp),%edi
 jmp set_SZV
 .align NALIGN,0x90
cb17: sahf
 rclb $1,%al
 movzbl %al,%edi
 jmp set_SZV
 .align NALIGN,0x90
cb18: sahf
 rcrb $1,%ch
 movzbl %ch,%edi
 jmp set_SZV
 .align NALIGN,0x90
cb19: sahf
 rcrb $1,%cl
 movzbl %cl,%edi
 jmp set_SZV
 .align NALIGN,0x90
cb1a: sahf
 rcrb $1,%dh
 movzbl %dh,%edi
 jmp set_SZV
 .align NALIGN,0x90
cb1b: sahf
 rcrb $1,%dl
 movzbl %dl,%edi
 jmp set_SZV
 .align NALIGN,0x90
cb1c: sahf
 rcrb $1,%bh
 movzbl %bh,%edi
 jmp set_SZV
 .align NALIGN,0x90
cb1d: sahf
 rcrb $1,%bl
 movzbl %bl,%edi
 jmp set_SZV
 .align NALIGN,0x90
cb1e: sahf
 rcrb $1,(%edi,%ebp)
 movzbl (%edi,%ebp),%edi
 jmp set_SZV
 .align NALIGN,0x90
cb1f: sahf
 rcrb $1,%al
 movzbl %al,%edi
 jmp set_SZV
 .align NALIGN,0x90
cb20: sahf
 shlb $1,%ch
 movzbl %ch,%edi
 jmp set_SZV
 .align NALIGN,0x90
cb21: sahf
 shlb $1,%cl
 movzbl %cl,%edi
 jmp set_SZV
 .align NALIGN,0x90
cb22: sahf
 shlb $1,%dh
 movzbl %dh,%edi
 jmp set_SZV
 .align NALIGN,0x90
cb23: sahf
 shlb $1,%dl
 movzbl %dl,%edi
 jmp set_SZV
 .align NALIGN,0x90
cb24: sahf
 shlb $1,%bh
 movzbl %bh,%edi
 jmp set_SZV
 .align NALIGN,0x90
cb25: sahf
 shlb $1,%bl
 movzbl %bl,%edi
 jmp set_SZV
 .align NALIGN,0x90
cb26: sahf
 shlb $1,(%edi,%ebp)
 movzbl (%edi,%ebp),%edi
 jmp set_SZV
 .align NALIGN,0x90
cb27: sahf
 shlb $1,%al
 movzbl %al,%edi
 jmp set_SZV
 .align NALIGN,0x90
cb28: sahf
 sarb $1,%ch
 movzbl %ch,%edi
 jmp set_SZV
 .align NALIGN,0x90
cb29: sahf
 sarb $1,%cl
 movzbl %cl,%edi
 jmp set_SZV
 .align NALIGN,0x90
cb2a: sahf
 sarb $1,%dh
 movzbl %dh,%edi
 jmp set_SZV
 .align NALIGN,0x90
cb2b: sahf
 sarb $1,%dl
 movzbl %dl,%edi
 jmp set_SZV
 .align NALIGN,0x90
cb2c: sahf
 sarb $1,%bh
 movzbl %bh,%edi
 jmp set_SZV
 .align NALIGN,0x90
cb2d: sahf
 sarb $1,%bl
 movzbl %bl,%edi
 jmp set_SZV
 .align NALIGN,0x90
cb2e: sahf
 sarb $1,(%edi,%ebp)
 movzbl (%edi,%ebp),%edi
 jmp set_SZV
 .align NALIGN,0x90
cb2f: sahf
 sarb $1,%al
 movzbl %al,%edi
 jmp set_SZV
 .align NALIGN,0x90
cb38: sahf
 shrb $1,%ch
 movzbl %ch,%edi
 jmp set_SZV
 .align NALIGN,0x90
cb39: sahf
 shrb $1,%cl
 movzbl %cl,%edi
 jmp set_SZV
 .align NALIGN,0x90
cb3a: sahf
 shrb $1,%dh
 movzbl %dh,%edi
 jmp set_SZV
 .align NALIGN,0x90
cb3b: sahf
 shrb $1,%dl
 movzbl %dl,%edi
 jmp set_SZV
 .align NALIGN,0x90
cb3c: sahf
 shrb $1,%bh
 movzbl %bh,%edi
 jmp set_SZV
 .align NALIGN,0x90
cb3d: sahf
 shrb $1,%bl
 movzbl %bl,%edi
 jmp set_SZV
 .align NALIGN,0x90
cb3e: sahf
 shrb $1,(%edi,%ebp)
 movzbl (%edi,%ebp),%edi
 jmp set_SZV
 .align NALIGN,0x90
cb3f: sahf
 shrb $1,%al
 movzbl %al,%edi
 jmp set_SZV
 .align NALIGN,0x90
cb40: testb $1,%ch
 jmp setbit
 .align NALIGN,0x90
cb41: testb $1,%cl
 jmp setbit
 .align NALIGN,0x90
cb42: testb $1,%dh
 jmp setbit
 .align NALIGN,0x90
cb43: testb $1,%dl
 jmp setbit
 .align NALIGN,0x90
cb44: testb $1,%bh
 jmp setbit
 .align NALIGN,0x90
cb45: testb $1,%bl
 jmp setbit
 .align NALIGN,0x90
cb46: testb $1,(%edi,%ebp)
 jmp setbit
 .align NALIGN,0x90
cb47: testb $1,%al
 jmp setbit
 .align NALIGN,0x90
cb48: testb $2,%ch
 jmp setbit
 .align NALIGN,0x90
cb49: testb $2,%cl
 jmp setbit
 .align NALIGN,0x90
cb4a: testb $2,%dh
 jmp setbit
 .align NALIGN,0x90
cb4b: testb $2,%dl
 jmp setbit
 .align NALIGN,0x90
cb4c: testb $2,%bh
 jmp setbit
 .align NALIGN,0x90
cb4d: testb $2,%bl
 jmp setbit
 .align NALIGN,0x90
cb4e: testb $2,(%edi,%ebp)
 jmp setbit
 .align NALIGN,0x90
cb4f: testb $2,%al
 jmp setbit
 .align NALIGN,0x90
cb50: testb $4,%ch
 jmp setbit
 .align NALIGN,0x90
cb51: testb $4,%cl
 jmp setbit
 .align NALIGN,0x90
cb52: testb $4,%dh
 jmp setbit
 .align NALIGN,0x90
cb53: testb $4,%dl
 jmp setbit
 .align NALIGN,0x90
cb54: testb $4,%bh
 jmp setbit
 .align NALIGN,0x90
cb55: testb $4,%bl
 jmp setbit
 .align NALIGN,0x90
cb56: testb $4,(%edi,%ebp)
 jmp setbit
 .align NALIGN,0x90
cb57: testb $4,%al
 jmp setbit
 .align NALIGN,0x90
cb58: testb $8,%ch
 jmp setbit
 .align NALIGN,0x90
cb59: testb $8,%cl
 jmp setbit
 .align NALIGN,0x90
cb5a: testb $8,%dh
 jmp setbit
 .align NALIGN,0x90
cb5b: testb $8,%dl
 jmp setbit
 .align NALIGN,0x90
cb5c: testb $8,%bh
 jmp setbit
 .align NALIGN,0x90
cb5d: testb $8,%bl
 jmp setbit
 .align NALIGN,0x90
cb5e: testb $8,(%edi,%ebp)
 jmp setbit
 .align NALIGN,0x90
cb5f: testb $8,%al
 jmp setbit
 .align NALIGN,0x90
cb60: testb $16,%ch
 jmp setbit
 .align NALIGN,0x90
cb61: testb $16,%cl
 jmp setbit
 .align NALIGN,0x90
cb62: testb $16,%dh
 jmp setbit
 .align NALIGN,0x90
cb63: testb $16,%dl
 jmp setbit
 .align NALIGN,0x90
cb64: testb $16,%bh
 jmp setbit
 .align NALIGN,0x90
cb65: testb $16,%bl
 jmp setbit
 .align NALIGN,0x90
cb66: testb $16,(%edi,%ebp)
 jmp setbit
 .align NALIGN,0x90
cb67: testb $16,%al
 jmp setbit
 .align NALIGN,0x90
cb68: testb $32,%ch
 jmp setbit
 .align NALIGN,0x90
cb69: testb $32,%cl
 jmp setbit
 .align NALIGN,0x90
cb6a: testb $32,%dh
 jmp setbit
 .align NALIGN,0x90
cb6b: testb $32,%dl
 jmp setbit
 .align NALIGN,0x90
cb6c: testb $32,%bh
 jmp setbit
 .align NALIGN,0x90
cb6d: testb $32,%bl
 jmp setbit
 .align NALIGN,0x90
cb6e: testb $32,(%edi,%ebp)
 jmp setbit
 .align NALIGN,0x90
cb6f: testb $32,%al
 jmp setbit
 .align NALIGN,0x90
cb70: testb $64,%ch
 jmp setbit
 .align NALIGN,0x90
cb71: testb $64,%cl
 jmp setbit
 .align NALIGN,0x90
cb72: testb $64,%dh
 jmp setbit
 .align NALIGN,0x90
cb73: testb $64,%dl
 jmp setbit
 .align NALIGN,0x90
cb74: testb $64,%bh
 jmp setbit
 .align NALIGN,0x90
cb75: testb $64,%bl
 jmp setbit
 .align NALIGN,0x90
cb76: testb $64,(%edi,%ebp)
 jmp setbit
 .align NALIGN,0x90
cb77: testb $64,%al
 jmp setbit
 .align NALIGN,0x90
cb78: testb $128,%ch
 jmp setbit
 .align NALIGN,0x90
cb79: testb $128,%cl
 jmp setbit
 .align NALIGN,0x90
cb7a: testb $128,%dh
 jmp setbit
 .align NALIGN,0x90
cb7b: testb $128,%dl
 jmp setbit
 .align NALIGN,0x90
cb7c: testb $128,%bh
 jmp setbit
 .align NALIGN,0x90
cb7d: testb $128,%bl
 jmp setbit
 .align NALIGN,0x90
cb7e: testb $128,(%edi,%ebp)
 jmp setbit
 .align NALIGN,0x90
cb7f: testb $128,%al
 jmp setbit
 .align NALIGN,0x90
cb80: andb $254,%ch
 dispatch
 .align NALIGN,0x90
cb81: andb $254,%cl
 dispatch
 .align NALIGN,0x90
cb82: andb $254,%dh
 dispatch
 .align NALIGN,0x90
cb83: andb $254,%dl
 dispatch
 .align NALIGN,0x90
cb84: andb $254,%bh
 dispatch
 .align NALIGN,0x90
cb85: andb $254,%bl
 dispatch
 .align NALIGN,0x90
cb86: andb $254,(%edi,%ebp)
 dispatch
 .align NALIGN,0x90
cb87: andb $254,%al
 dispatch
 .align NALIGN,0x90
cb88: andb $253,%ch
 dispatch
 .align NALIGN,0x90
cb89: andb $253,%cl
 dispatch
 .align NALIGN,0x90
cb8a: andb $253,%dh
 dispatch
 .align NALIGN,0x90
cb8b: andb $253,%dl
 dispatch
 .align NALIGN,0x90
cb8c: andb $253,%bh
 dispatch
 .align NALIGN,0x90
cb8d: andb $253,%bl
 dispatch
 .align NALIGN,0x90
cb8e: andb $253,(%edi,%ebp)
 dispatch
 .align NALIGN,0x90
cb8f: andb $253,%al
 dispatch
 .align NALIGN,0x90
cb90: andb $251,%ch
 dispatch
 .align NALIGN,0x90
cb91: andb $251,%cl
 dispatch
 .align NALIGN,0x90
cb92: andb $251,%dh
 dispatch
 .align NALIGN,0x90
cb93: andb $251,%dl
 dispatch
 .align NALIGN,0x90
cb94: andb $251,%bh
 dispatch
 .align NALIGN,0x90
cb95: andb $251,%bl
 dispatch
 .align NALIGN,0x90
cb96: andb $251,(%edi,%ebp)
 dispatch
 .align NALIGN,0x90
cb97: andb $251,%al
 dispatch
 .align NALIGN,0x90
cb98: andb $247,%ch
 dispatch
 .align NALIGN,0x90
cb99: andb $247,%cl
 dispatch
 .align NALIGN,0x90
cb9a: andb $247,%dh
 dispatch
 .align NALIGN,0x90
cb9b: andb $247,%dl
 dispatch
 .align NALIGN,0x90
cb9c: andb $247,%bh
 dispatch
 .align NALIGN,0x90
cb9d: andb $247,%bl
 dispatch
 .align NALIGN,0x90
cb9e: andb $247,(%edi,%ebp)
 dispatch
 .align NALIGN,0x90
cb9f: andb $247,%al
 dispatch
 .align NALIGN,0x90
cba0: andb $239,%ch
 dispatch
 .align NALIGN,0x90
cba1: andb $239,%cl
 dispatch
 .align NALIGN,0x90
cba2: andb $239,%dh
 dispatch
 .align NALIGN,0x90
cba3: andb $239,%dl
 dispatch
 .align NALIGN,0x90
cba4: andb $239,%bh
 dispatch
 .align NALIGN,0x90
cba5: andb $239,%bl
 dispatch
 .align NALIGN,0x90
cba6: andb $239,(%edi,%ebp)
 dispatch
 .align NALIGN,0x90
cba7: andb $239,%al
 dispatch
 .align NALIGN,0x90
cba8: andb $223,%ch
 dispatch
 .align NALIGN,0x90
cba9: andb $223,%cl
 dispatch
 .align NALIGN,0x90
cbaa: andb $223,%dh
 dispatch
 .align NALIGN,0x90
cbab: andb $223,%dl
 dispatch
 .align NALIGN,0x90
cbac: andb $223,%bh
 dispatch
 .align NALIGN,0x90
cbad: andb $223,%bl
 dispatch
 .align NALIGN,0x90
cbae: andb $223,(%edi,%ebp)
 dispatch
 .align NALIGN,0x90
cbaf: andb $223,%al
 dispatch
 .align NALIGN,0x90
cbb0: andb $191,%ch
 dispatch
 .align NALIGN,0x90
cbb1: andb $191,%cl
 dispatch
 .align NALIGN,0x90
cbb2: andb $191,%dh
 dispatch
 .align NALIGN,0x90
cbb3: andb $191,%dl
 dispatch
 .align NALIGN,0x90
cbb4: andb $191,%bh
 dispatch
 .align NALIGN,0x90
cbb5: andb $191,%bl
 dispatch
 .align NALIGN,0x90
cbb6: andb $191,(%edi,%ebp)
 dispatch
 .align NALIGN,0x90
cbb7: andb $191,%al
 dispatch
 .align NALIGN,0x90
cbb8: andb $127,%ch
 dispatch
 .align NALIGN,0x90
cbb9: andb $127,%cl
 dispatch
 .align NALIGN,0x90
cbba: andb $127,%dh
 dispatch
 .align NALIGN,0x90
cbbb: andb $127,%dl
 dispatch
 .align NALIGN,0x90
cbbc: andb $127,%bh
 dispatch
 .align NALIGN,0x90
cbbd: andb $127,%bl
 dispatch
 .align NALIGN,0x90
cbbe: andb $127,(%edi,%ebp)
 dispatch
 .align NALIGN,0x90
cbbf: andb $127,%al
 dispatch
 .align NALIGN,0x90
cbc0: orb $1,%ch
 dispatch
 .align NALIGN,0x90
cbc1: orb $1,%cl
 dispatch
 .align NALIGN,0x90
cbc2: orb $1,%dh
 dispatch
 .align NALIGN,0x90
cbc3: orb $1,%dl
 dispatch
 .align NALIGN,0x90
cbc4: orb $1,%bh
 dispatch
 .align NALIGN,0x90
cbc5: orb $1,%bl
 dispatch
 .align NALIGN,0x90
cbc6: orb $1,(%edi,%ebp)
 dispatch
 .align NALIGN,0x90
cbc7: orb $1,%al
 dispatch
 .align NALIGN,0x90
cbc8: orb $2,%ch
 dispatch
 .align NALIGN,0x90
cbc9: orb $2,%cl
 dispatch
 .align NALIGN,0x90
cbca: orb $2,%dh
 dispatch
 .align NALIGN,0x90
cbcb: orb $2,%dl
 dispatch
 .align NALIGN,0x90
cbcc: orb $2,%bh
 dispatch
 .align NALIGN,0x90
cbcd: orb $2,%bl
 dispatch
 .align NALIGN,0x90
cbce: orb $2,(%edi,%ebp)
 dispatch
 .align NALIGN,0x90
cbcf: orb $2,%al
 dispatch
 .align NALIGN,0x90
cbd0: orb $4,%ch
 dispatch
 .align NALIGN,0x90
cbd1: orb $4,%cl
 dispatch
 .align NALIGN,0x90
cbd2: orb $4,%dh
 dispatch
 .align NALIGN,0x90
cbd3: orb $4,%dl
 dispatch
 .align NALIGN,0x90
cbd4: orb $4,%bh
 dispatch
 .align NALIGN,0x90
cbd5: orb $4,%bl
 dispatch
 .align NALIGN,0x90
cbd6: orb $4,(%edi,%ebp)
 dispatch
 .align NALIGN,0x90
cbd7: orb $4,%al
 dispatch
 .align NALIGN,0x90
cbd8: orb $8,%ch
 dispatch
 .align NALIGN,0x90
cbd9: orb $8,%cl
 dispatch
 .align NALIGN,0x90
cbda: orb $8,%dh
 dispatch
 .align NALIGN,0x90
cbdb: orb $8,%dl
 dispatch
 .align NALIGN,0x90
cbdc: orb $8,%bh
 dispatch
 .align NALIGN,0x90
cbdd: orb $8,%bl
 dispatch
 .align NALIGN,0x90
cbde: orb $8,(%edi,%ebp)
 dispatch
 .align NALIGN,0x90
cbdf: orb $8,%al
 dispatch
 .align NALIGN,0x90
cbe0: orb $16,%ch
 dispatch
 .align NALIGN,0x90
cbe1: orb $16,%cl
 dispatch
 .align NALIGN,0x90
cbe2: orb $16,%dh
 dispatch
 .align NALIGN,0x90
cbe3: orb $16,%dl
 dispatch
 .align NALIGN,0x90
cbe4: orb $16,%bh
 dispatch
 .align NALIGN,0x90
cbe5: orb $16,%bl
 dispatch
 .align NALIGN,0x90
cbe6: orb $16,(%edi,%ebp)
 dispatch
 .align NALIGN,0x90
cbe7: orb $16,%al
 dispatch
 .align NALIGN,0x90
cbe8: orb $32,%ch
 dispatch
 .align NALIGN,0x90
cbe9: orb $32,%cl
 dispatch
 .align NALIGN,0x90
cbea: orb $32,%dh
 dispatch
 .align NALIGN,0x90
cbeb: orb $32,%dl
 dispatch
 .align NALIGN,0x90
cbec: orb $32,%bh
 dispatch
 .align NALIGN,0x90
cbed: orb $32,%bl
 dispatch
 .align NALIGN,0x90
cbee: orb $32,(%edi,%ebp)
 dispatch
 .align NALIGN,0x90
cbef: orb $32,%al
 dispatch
 .align NALIGN,0x90
cbf0: orb $64,%ch
 dispatch
 .align NALIGN,0x90
cbf1: orb $64,%cl
 dispatch
 .align NALIGN,0x90
cbf2: orb $64,%dh
 dispatch
 .align NALIGN,0x90
cbf3: orb $64,%dl
 dispatch
 .align NALIGN,0x90
cbf4: orb $64,%bh
 dispatch
 .align NALIGN,0x90
cbf5: orb $64,%bl
 dispatch
 .align NALIGN,0x90
cbf6: orb $64,(%edi,%ebp)
 dispatch
 .align NALIGN,0x90
cbf7: orb $64,%al
 dispatch
 .align NALIGN,0x90
cbf8: orb $128,%ch
 dispatch
 .align NALIGN,0x90
cbf9: orb $128,%cl
 dispatch
 .align NALIGN,0x90
cbfa: orb $128,%dh
 dispatch
 .align NALIGN,0x90
cbfb: orb $128,%dl
 dispatch
 .align NALIGN,0x90
cbfc: orb $128,%bh
 dispatch
 .align NALIGN,0x90
cbfd: orb $128,%bl
 dispatch
 .align NALIGN,0x90
cbfe: orb $128,(%edi,%ebp)
 dispatch
 .align NALIGN,0x90
cbff: orb $128,%al
 dispatch