+5V +5V2 +5V3 +5V4 SEG 0COUNT 6COUNT 700 701 702 704 706 707 708 709 710 711 712 715 720 721 722 725 727 730 732 733 742 750 754 770 773 774 775 776 777 782 783 785 786 787 790 792 793 797 798 7120 7125 7126 7133 7134 7136 7138 7139 7147 7148 7150 74150A 74150B 7153 7154 74154A 74154B 7155 7155A 7157 7158 7160 7161 7162 7163 7168 7169 7174 7175 7175A 7192 7193 7244 7245 7373 7374 ND ND3 ND4 ND8 NDX NDX3 NDX4 ARROW1 ARROW2 SCDISP SCKBD REAK CIRC CIRC1 CIRC2 LOCK OMPL OMPL2 CROSS2 CROSS3 CROSS4 CROSS5 CRUNCH CRUNCH2 IGH NEG POS DTOA DGE ORCEDRVFROM DNEG DPOS GINST1 GINST2 GINST3 GINST4 GINST5 GND NST0 NST1 NST2 NST3 NST4 NST5 NV NV4 NV4A NVX KNEG KPOS JUMPER JUMPER2 JUMPER3 JUMPER4 JUMPER5 JUMPER6 EYPAD ATCH ED ED2 ED3 AND AND3 AND4 AND8 ANDX ANDX3 ANDX4 OR OR3 OR4 OR8 ORX ORX3 ORX4 OLDGND OLDTIME R R3 R4 R8 RX RX3 RX4 ULSE COPE HIFT RAM8K SW2 SW4 WCOMPL WITCH WITCH2 IE IEGND TIME NEG TO POS VDD V_AN V_AN3 V_BU V_CSL V_CSL0 V_CSL2 V_CSL4 V_CSLN V_IN V_NAD V_NAD3 V_NFT V_NFTD V_NFTD2V_NFTX V_NFTX2V_NFTZ V_NO V_NO3 V_OR V_OR V_PFT V_PFTD V_PFTD2V_PFTX V_PFTX2V_PFTZ V_TRNS V_TRNSNNOR OR @  \ z  % e     A v       P p   N     "5 ' ; # \$      "   f         _  /$ < [ % ! 1!)   #  N   )'(    (  w # D m* ". %k "  ,, .  ' r  "! ) & * ) , D,    7   ,  p+  &  l)' !' a"'        6 `      , !X 1C!  ! "" ""."g """ " "" " " S#a& #% $ $! $4$B$F, $+ %  %@ %{%$&* &&P &W  &  &# '  'R$ '*  &' ((V( () )* )r  )~ )))))?)#  ***A*X*h *** + += +j + + +, ,T ,{ ,, ,)-  -3 -H-b - - - .  .#.A .1A $/* `/9@/Z  /~ // /  /0,$ 00# 0  0  1  19 1] 1 1  1$ -2 2K 2o 22  2 2@ 2 2@ 3 31  3`  3  3  3 4 49@ 4^ 4@ 44 4 5  54  This is the standard "Vcc" or "Vdd" source.Vdd    Identical to +5V, but rotated.R:Stupid2I42:IntegerVddVdd         Vdd   jkl­míLOGSIM_LOG_16_7SEGvv v  v vv v v v v v v v v vvvvv v v v  vvvvvvvvvv vv vvCBCD counter with asynchronous clear, set-to-9.pqrsぃƐ"#$%vv v  v vv v v v v v v v v vvvv v v v  vvv vvv vvvvCBinary counter, with asynchronous clear.pqrs"#$%v vv v v vv  v  v  v vvvC 2-input NAND."v vv v v vv  v  v  v vvvv C 2-input NAND, open-collector.Bvvv v vvvv v vv vvvC 2-input NOR."v v vv vC Inverter.!!v v vv vvC Inverter, open-collector.AA  Non-inverting buffer, open-collector.AA           2-input AND."            2-input AND, open-collector.Bvvvv vv v v  v vv v  vC  3-input NAND.#        3-input AND.#vvvv vv v v  v vv v  vvC  3-input NAND, open-collector.C        3-input AND, open-collector.Cvvv v v v v  v  v vvvvvvC 4-input NAND.$        4-input AND.$vvv v v v v  v  v vvvvvvvC 4-input NAND, open-collector.Dvv v v vvvvvv vvvv v vvvv vC 4-input NOR with strobe.Output is low if any input = 1, and strobe = 1.$Ţvvv vvvv v  v vvvvv vC  3-input NOR.#vvv v v v v  v vvvvvvvvv vvC  8-input NAND.`(ĠŠƠ      2-input OR."vvv v vvvv v vv vvvv C 2-input NOR, open collector.B                   4-to-10 decoder. Outputs are active-low. D is MSB. !"#$%&'()HGFEDCBA@Ivvvvvvvvvvvv v vvvvvvvv v  v  v v v vvvvv v vvvvvC vAND-OR-INVERT network.$vvvvvv vvvvvvvvvvvvvvv v v v vvv vvvv v vvv vvvv v vv  v v vvvvvvvvvvvvvvC AND-OR-INVERT network.`(Ţvv v  v vvvvv vv v  vvvvvvvvvvvv v vvvvvvCC CC  C  Positive edge triggered J-K flip-flop with asynchronous preset, clear.J and preset are at top (with non-inverted output).Internal J and K are AND of two plain and one inverted input.iǥj ȥpŐƀ#$vv v  v vvvvv v v  vvvvvvvCC  C  Negative edge triggered J-K flip-flop with asynchronous clear.J is at top (with non-inverted output).€pŀ#$vv v  v vvvv vvv vvvvvvCC CPositive edge-triggered Data flip-flop with asynchronous preset, clear.`Đŀ"#vv v  v vv v v  v v vvvvvvvC    Latch. If clock is high, output follows input, else output holds.`"#vv v  v vvvvvv v v  vvvvvvvvCCCC    Negative edge triggered J-K flip-flop, with asynchronous preset, clear.J is at top (with non-inverted output).€pŐƀ#$      Latch. If clock is high, output follows input, else output holds.`"          2-bit full adder. Carry input at top, carry output at bottom, top is LSB.%b Ģ&'à                 4-bit full adder. Carry input at top, carry output at bottom, top is LSB.)bĠȢ*bŠ+¤bƠ,ä-Ǡ         4-bit magnitude comparator. Left pins are MSBs. Outputs on left are left value <, =, and > right value. Carry inputs are on the right.`a`a`a`a-,+-,+-,+      2-input Exclusive OR."          Quad 1-0-true-invert element. Depending on control pins, outputs on right are 00 Inverse of input 01 Input 10 One 11 Zero&'()vv v  v v v v v vvvvvvvvv v v vvvvvvvvvvv vCC BCD counter. Internal clear and set-to-nine are AND of input pins.Clear and MSB are at the bottom.Clock at left controls only LSB. Clock at top controls other 3 bits.Connect top clock to closest output for full BCD counter.pdɄe䠧qrsぃǀȐ"#$%vv v  v v v v v vvvvv v v vvvvvvv vvvvvvCC Twelve-counter. Internal clear is AND of two input pins. MSB is at bottom.Clock at left controls only LSB. Clock at top controls other 3 bits.Connect top clock to closest output for full 12-counter.Sequence for 3 high bits is 000-001-010-100-101-110.pdƄe䠧qr⁂sǀ"#$%vv v  v v v v v vvvvv v v vvvvvvv vvvvvCC Binary counter. Internal clear is AND of two input pins. MSB is at bottom.Clock at left controls only LSB. Clock at top controls other 3 bits.Connect top clock to closest output for full binary counter.pdƄeqrsǀ"#$%vv v v vvvvvv vvv vvvvvvvvvvvvvCCCC C v 6-bit Rate Multiplier, with all sorts of inputs and outputs!Ʀpqrstùf)fffffff+*vv v v vvvvvvvvvvvvv vvvvvvv v  v v vv vvvvv C  Data selector/register. Register loads from inputs on falling edge of clock.Upper inputs are used if top pin is one, else lower inputs are used.`abc`abc*+,-vv v  v vvvvvvvvvvv v vvvv vv vv vv v v C  Clock synchronizer.€a`%&v v vvvvCTristate buffer. Floats if control is high.Hidden pin at bottom follows control input, for easily cascading buffers.!!#  Tri-state buffer. Floats if control input is low.Hidden pin at bottom follows control input, for easily cascading buffers.!!#vvvv v v v vvvvvvvvvvvvvvvvvvvv vvvvvvvvvv v C vv 13-input NAND.` `ŠƠ-ɠʠvvvv v v v vvvvvvvvvvvvvvvvvvvv vvvvvvvv v vC Cv 12-input NAND with tri-state output. Floats if control input is one.Hidden pin at bottom follows control input, for easily cascading gates.` `ŠƠ-ɠ       2-input Exclusive OR, open-collector.Bv v vv v v v v v v  v v vv vvvvvvvvvvvvvvCC  3-to-8 decoder. If gate pins are high/low/low, selected output goes low.0 and LSB at top, 7 and MSB at bottom.†ba`&'()*+,-v v vv v v v v vvvvvvvvvvvvvC2-to-4 decoder. If gate input is low, selected output goes low.0 and LSB at top, 3 and MSB at bottom.#$%&              Priority encoder. Output is inverted BCD number, MSB at bottom.Result is number of highest input which is low, or 0 (1111) if all high.`àĠƂa`ơȃ`)*+,               Priority encoder. Bottom pins are MSB and highest-priority input.If bottom pin is one, all outputs are one. Otherwise, result isinverted 3-bit code of highest-priority input which is low, and othertwo outputs go low (top-right) and high (top) if any input is low.Ǡƒ``àĠƃđ`Ɓ`(*+,-- -  ##((---2-2-2 - 2 #(222 2  Top half of 1-of-16 selector. Join to 74150A for complete chip.If strobe at top is low, selects data. If high, forces output high.````````````````5              Bottom half of 1-of-16 selector. Join to 74150B for complete chip.Left control pin is MSB. Output at right is inverted copy of selected input. ңhhiii좠`abcdefglmno-./0        Top half of 1-of-16 selector. Join to 74150A for complete chip.If strobe at top is low, selects data. If high, forces output high.`abcdefglmnohhiii좠-.jvvvvv v v v vvvvvvvvvvv v v vC1-of-4 selector. Left control pin is MSB. If strobe at top is high, forcesoutput at right low, else output follows selected input.''''Gv&v v -v vv v v v v vvvvvvv v vvvvvvv --v-&vv v v v v v v v# #v( (vvvvvvCC #( `abcdѭ !"#$%&'()*+,-./                     `abcΔd !"#$%&'             `abcΔd !"#$%&'v v v v vvvvvvvv v v vvvvv v v vvC2-to-4 decoder. If gate inputs are high/low, selected output goes low.CBA@v v v v vvvvvvvv v v vvvvv v v vvCC2-to-4 decoder. If gate inputs are low/low, selected output goes low.CBA@vv v  v vvvvvv vvv v v v vvvvvvvvvvC Quad 1-of-2 selector. If enable on right is high, all outputs go low,else outputs follow selected inputs (bottom if control on left is one).*+,-*+,-*+,-vv v  v vvvvvv vvv v v v vvvvvvvvvvvvCC C C  C   Quad 1-of-2 selector. If enable on right is high, all outputs go high,else outputs invert selected inputs (bottom if control on right is one).*+,-*+,-*+,-vv v v vv vvv vv v v  v vvvvv v v v  v vvvvvvvvvvvvvvvvCC  BCD counter. Clocks on rising edge. Synchronous load, asynchronous clear.Count is inhibited if left or bottom carry in is zero. Carry out is one ifcount is 9 and left carry in is one.defgpqr䢠s`abc̀%&'()vv v v vv vvv vv v v  v vvvvv v v v  v vvvvvvvvvvvvvCC  Binary counter. Clocks on rising edge. Synchronous load, asynchronous clear.Count is inhibited if left or bottom carry in is zero. Carry out is one ifcount is 15 and left carry in is one.defgpqrs`abc̀%&'()vv v v vv vvv vv v v  v vvvvv v v v  v vvvvvvvvvvvvvvvvvCC  BCD counter. Clocks on rising edge. Synchronous load and clear.Count is inhibited if left or bottom carry in is zero. Carry out is one ifcount is 9 and left carry in is one.defgpqr䢠s`abc̀%&'()vv v v vv vvv vv v v  v vvvvv v v v  v vvvvvvvvvvvvvvvvCC  Binary counter. Clocks on rising edge. Synchronous load and clear.Count is inhibited if left or bottom carry in is zero. Carry out is one ifcount is 15 and left carry in is one.defgpqrs`abc̀%&'()vv v v vv vvvvv v v  v vvvvv v v v  v vvvvvvvvvvvvvvvvvCCC C  BCD up/down counter. Clocks on rising edge. Synchronous load.Counts up if U is one, down is U is zero. Count is inhibited if eitherleft or bottom carry in is one. Carry out is zero if count is 9 (up) or0 (down), and left carry in is zero.defgpqrsぃpqrsあ`abch͢i%&'()vv v v vv vvvvv v v  v vvvvv v v v  v vvvvvvvvvvvvvvvvvCCC C  Binary up/down counter. Clocks on rising edge. Synchronous load.Counts up if U is one, down if U is zero. Count is inhibited if eitherleft or bottom carry in is one. Carry out is zero if count was 15 (up) or0 (down), and left carry in is zero.defgpqrspqrs`abch%&'()vvvvv v  v v v v v v v  vvvvvvvvvvv v v C  6-bit register. Asynchronous clear. Clocks on rising edge.`abcde()*+,-vvvvvv v  v v v v v v v  v v vvvvvvvvvvvvC 4-bit register. Alternate outputs are inverted. Asynchronous clear.Clocks on rising edge.`abc&'()*+,-vvvvvv v  v v v v v vvvvvvvvvvvvC4-bit register. Asynchronous clear. Clocks on rising edge.`abc&'()vv v v vv vvvvv v v  v vvvvv v vvvvvvvvvvvvvv v vvvvvvCCC   BCD counter. Clocks on rising edge. Synchronous load and clear.Count is inhibited if left or bottom carry in is zero. Carry out is one ifcount is 9 and left carry in is one.,ʡ-ˢcbapぃcbapあ`abc&'()vv v v vv vvvvv v v  v vvvvv v vvvvvvvvvvvvvvv v vvvvCCC   Binary counter. Clocks on rising edge. Synchronous load and clear.Count is inhibited if left or bottom carry in is zero. Carry out is one ifcount is 15 and left carry in is one.,ʡ-ˢcbapcbap`abc&'()                  Eight-bit tristate buffer. Upper four bits conduct left to right when toppin is low; bottom pin controls lower four bits. !"#$%&'                 Bidirectional buffer. If bottom pin is high, all pins are tri-state. If low,pins conduct left-to-right if top pin low, right-to-left if top pin high. !"#$%&'()*+,-./                   Eight-bit latch with tristate outputs. If top pin is high, outputs float. Iflow, outputs follow inputs for bottom pin high, latch for bottom pin low.`abcdefg !"#$%&'                   Eight-bit latch with tristate outputs. If top pin is high, outputs float. Iflow, outputs are enabled. Inputs are latched on rising edge of bottom pin.`abcdefg !"#$%&'           "      #       $       `(ĠŠƠvvv v v vv vvvvv vvCCC "vvv vvvv  vvv v  vvvv CCC C  #vv v v vvvv vvvv v vvvvvCCCCC $      ASCII terminal display.Lefthand pins are clear (above) and strobe (below).[auto-lf] BY:Auto LF on CR:[erase-bs] BN:Erase on backspace:[auto-wrap] BY:Auto wrap at EOL:`abcdefghiMYGATES_ASCDISPvDvvDvvvvvvv vvvDDtF1tF2tF3tF4tF5tF6tF7tF8tF9tF&0tF0-tF:=tFQtFWtFEtFRtFTtFYtFUtFItFOtF&PtF0[tF:]tFAtFStFDtFFtFGtFHtFJtFKtFLtF&;tF0'tFZtFXtFCtFVtFBtFNtFMtF,tF.tF&/vv!v!!v!v:8v88v8:v::v: