A_AND A_ANDA A_ANDB A_AND A_ANDA A_ANDB A_ANDC A_AND A_ANDA A_ANDB A_ANDC A_ANDD A_AO1 A_AO1 A_AO1 A_AO1 A_AO2 A_AO2 A_AOIA A_AOIB A_AOIA A_AOIB A_AX1 A_AX1 A_AX1 A_BIBF A_BUF A_BUF A_CLKUFA_CLOK A_DF1 A_DF1 A_DF1 A_DF1 A_DFC A_DFCA A_DFCB A_DFCC A_DFCD A_DFCE A_DFCF A_DFCG A_DFE A_DFE A_DFE A_DFE A_DFE A_DFM A_DFM A_DFM A_DFP A_DFPA A_DFPB A_DFPC A_DFPD A_DFPE A_DFPF A_DFPG A_DFP A_DFPA A_DL1 A_DL1 A_DL1 A_DL1 A_DLC A_DLC A_DLE A_DLE A_DLE A_DLE A_DLM A_DLM A_FA1 A_FA1 A_HA1 A_HA1 A_HA1 A_HA1 A_INBF A_INV A_INV A_JKF A_JKFC A_MAJ A_MX2 A_MX2 A_MX2 A_MX2 A_MX4 A_MXT A_NAN2 A_NAN2AA_NAN2BA_NAN3 A_NAN3AA_NAN3BA_NAN3CA_NAN4 A_NAN4AA_NAN4BA_NAN4CA_NAN4DA_NOR A_NORA A_NORB A_NOR A_NORA A_NORB A_NORC A_NOR A_NORA A_NORB A_NORC A_NORD A_OA1 A_OA1 A_OA1 A_OA1 A_OA2 A_OA2 A_OA3 A_OA3 A_OA3 A_OR2 A_OR2 A_OR2 A_OR3 A_OR3 A_OR3 A_OR3 A_OR4 A_OR4 A_OR4 A_OR4 A_OR4 A_OUTUFA_TFC A_TRIUFA_XA1 A_XA1 A_XNO A_XO1 A_XO1 A_XOR      "  Y      ;y   - j    &e     & h     .  p            <   b            2  ^      "  ,  c  +  "+  M  -  2 -4     3 e  "  < }     3 l!   & f% 1  / Z"     < y         (O62  <! x! $ ! 6!      %`   F <  r       O   ; v    !  K  v    #     5  c        8  o         T     !  !O   !h !  !  !  "  "5  "_  "  v vv vvv c c  ACTEL logic gate.C:Gate name:C:Options:"v vv vvv c c  eACTEL logic gate.C:Gate name:C:Options:"v vv vvv c c  eeACTEL logic gate.C:Gate name:C:Options:"vv vvv vvc c   ACTEL logic gate.C:Gate name:C:Options:#vvvv vvv c c  e ACTEL logic gate.C:Gate name:C:Options:#vvvv vvv c c  ee ACTEL logic gate.C:Gate name:C:Options:#£vvvv vvv c c  eee  ACTEL logic gate.C:Gate name:C:Options:#vvvvvvvv vvvvvc c   ACTEL logic gate.C:Gate name:C:Options:$vvvvvvvv vvvvvc c   eACTEL logic gate.C:Gate name:C:Options:$vvvvvvvv c c   eeACTEL logic gate.C:Gate name:C:Options:$vvvvvvvv c c   eeeACTEL logic gate.C:Gate name:C:Options:$¥vvvvvvvv vvvvvc c   eeee ACTEL logic gate.C:Gate name:C:Options:$vvvvvvvccc c  v  vc ACTEL logic gate.C:Gate name:C:Options:#vvvvv  vvvvccc c c  eACTEL logic gate.C:Gate name:C:Options:#vvvvv  vvvvccc c  c eACTEL logic gate.C:Gate name:C:Options:#vvvvv  vvvvccc c c  eeACTEL logic gate.C:Gate name:C:Options:#vvvvvvvvvvccc c c  ACTEL logic gate.C:Gate name:C:Options:$vvvvvvvvvvccc c  c eACTEL logic gate.C:Gate name:C:Options:$vvvvv  vvvccc c c  eevACTEL logic gate.C:Gate name:C:Options:#vvvvv  vvvvccc c c  eeACTEL logic gate.C:Gate name:C:Options:#vvvvvvvvvvccc c c  eeACTEL logic gate.C:Gate name:C:Options:$vvvvvvvvvvccc c  c eeeACTEL logic gate.C:Gate name:C:Options:$vvvvvvvccc c vv  c c eACTEL logic gate.C:Gate name:C:Options:#vvvvv  vvvvccc c c c eeACTEL logic gate.C:Gate name:C:Options:#vvvvv  vvvvccc c c c eeACTEL logic gate.C:Gate name:C:Options:#        ACTEL bidirectional pad buffer.If control pin is high, drives pad out. Else acts as input.C:Gate name:C:Options: # ACTEL logic gate.C:Gate name:C:Options:!    ACTEL logic gate.C:Gate name:C:Options:! ACTEL clock pad buffer.To drive the input, connect a switch to the red dot on the pad.C:Gate name:C:Options:    Handy connection to node "CLK".CLK      ACTEL flip-flop.C:Gate name:C:Options:`"        ACTEL flip-flop.C:Gate name:C:Options:`"         ACTEL flip-flop.C:Gate name:C:Options:`"          ACTEL flip-flop.C:Gate name:C:Options:`"      ACTEL flip-flop with clear.C:Gate name:C:Options:`À"         ACTEL flip-flop with clear.C:Gate name:C:Options:`À"      ACTEL flip-flop with clear.C:Gate name:C:Options:`À"        ACTEL flip-flop with clear.C:Gate name:C:Options:`À"         ACTEL flip-flop with clear.C:Gate name:C:Options:`À"        ACTEL flip-flop with clear.C:Gate name:C:Options:`À"          ACTEL flip-flop with clear.C:Gate name:C:Options:`À"          ACTEL flip-flop with clear.C:Gate name:C:Options:`À"      ACTEL flip-flop with enable.Reads data input on rising clock edge only if E is high.C:Gate name:C:Options:`"        ACTEL flip-flop with enable.Reads data on falling clock edge only if E is high.C:Gate name:C:Options:`"      ACTEL flip-flop with enable, preset, and clear.Reads data on rising clock edge only if E is high.Preset and clear override clock and enable.C:Gate name:C:Options:`ĀŐ""        ACTEL flip-flop with enable, preset, and clear.Reads data on falling clock edge only if E is high.Preset and clear override clock and enable.C:Gate name:C:Options:`ĀŐ""      ACTEL flip-flop with enable.Reads data on rising clock edge only if E is low.C:Gate name:C:Options:`"      ACTEL flip-flop with multiplexer.If select is low, reads upper input on rising clock edge.If select is high, reads lower input on rising clock edge.C:Gate name:C:Options:``$        ACTEL flip-flop with multiplexer.If select is low, reads from upper data input on falling clock edge.If select is high, reads from lower data input on falling clock edge.C:Gate name:C:Options:``$      ACTEL flip-flop with multiplexer and clear.If select is low, reads from upper data input on rising clock edge.If select is high, reads from lower data input on rising clock edge.C:Gate name:C:Options:``ŀ$      ACTEL flip-flop with preset.C:Gate name:C:Options:`Ð"         ACTEL flip-flop with preset.C:Gate name:C:Options:`Ð"      ACTEL flip-flop with preset.C:Gate name:C:Options:`Ð"        ACTEL flip-flop with preset.C:Gate name:C:Options:`Ð"        ACTEL flip-flop with preset.C:Gate name:C:Options:`Ð"       ACTEL flip-flop with preset.C:Gate name:C:Options:`Ð"         ACTEL flip-flop with preset.C:Gate name:C:Options:`Ð"         ACTEL flip-flop with preset.C:Gate name:C:Options:`Ð"      ACTEL flip-flop with preset and clear.Preset and clear override clock.C:Gate name:C:Options:`ÀĐ""        ACTEL flip-flop with preset and clear.Preset and clear override clock.C:Gate name:C:Options:`ÀĐ""      ACTEL level-sensitive latch.C:Gate name:C:Options:`"       ACTEL level-sensitive latch.C:Gate name:C:Options:`"        ACTEL level-sensitive latch.C:Gate name:C:Options:`"         ACTEL level-sensitive latch.C:Gate name:C:Options:`"      ACTEL level-sensitive latch with clear.Clear overrides G input.C:Gate name:C:Options:`À"        ACTEL level-sensitive latch with clear.Clear overrides G input.C:Gate name:C:Options:`À"      ACTEL level-sensitive latch with enable.Latches with E and G are both high.C:Gate name:C:Options:`"      ACTEL level-sensitive latch with enable.Latches when E is low and G is high.C:Gate name:C:Options:`"        ACTEL level-sensitive latch with enable.Latches when E is high and G is low.C:Gate name:C:Options:`"        ACTEL level-sensitive latch with enable.Latches when E and G are both low.C:Gate name:C:Options:`"      ACTEL level-sensitive data latch with multiplexer.If select is low and G is high, latches upper data input.If select is high and G is high, latches lower data input.C:Gate name:C:Options:``$       ACTEL level-sensitive latch with multiplexer.If select is low and G is low, latches upper data input.If select is high and G is low, latches lower data input.C:Gate name:C:Options:``$            ACTEL full adder.Upper output is (inverted) carry, lower output is sum.C:Gate name:C:Options:`#$            ACTEL full adder.Upper output is (inverted) carry, lower output is sum.C:Gate name:C:Options:`#$      ACTEL half adder.Upper output is carry, lower output is sum.C:Gate name:C:Options:"#      ACTEL half adder.Upper output is carry, lower output is sum.C:Gate name:C:Options:"#                ACTEL half adder.Upper output is inverted carry, lower output is inverted sum.C:Gate name:C:Options:"#         ACTEL half adder.Upper output is carry, lower output is sum.C:Gate name:C:Options:"# ACTEL input pad buffer.To drive in simulation, connect a switch to the red dot on the pad.C:Gate name:C:Options:   ACTEL logic gate.C:Gate name:C:Options:! ACTEL logic gate.C:Gate name:C:Options:!        ACTEL J-K flip-flop.When JK inputs are 01 -> no change, 10 -> toggle, 11 -> set flip-flop, 00 -> clear flip-flop.C:Gate name:C:Options:a``#        ACTEL J-K flip-flop with preset and clear.When JK inputs are 01 -> no change, 10 -> toggle, 11 -> set flip-flop, 00 -> clear.Preset and clear inputs override the clock.C:Gate name:C:Options:a``Đŀ##       ACTEL majority gate. Output is 1 or 0, depending on whether moreof the inputs are 1 or 0.C:Gate name:C:Options:#     ACTEL multiplexer.If select is low, uses upper input. If select is high, uses lower input.C:Gate name:C:Options:##    ACTEL multiplexer.If select is low, uses (inverted) upper input. If select is high,uses lower input.C:Gate name:C:Options:##     ACTEL multiplexer.If select is low, uses upper input. If select is high, uses (inverted)lower input.C:Gate name:C:Options:##       ACTEL multiplexer.If select is low, uses (inverted) upper input. If select is high, uses(inverted) lower input.C:Gate name:C:Options:##   ACTEL multiplexer.Left select bit is MSB, right select bit is LSB. Top input is 00, bottominput is 11.C:Gate name:C:Options:&&&&      ACTEL general multiplexer.For each mux, low select chooses upper input, high select chooses lower input.C:Gate name:C:Options:''''v vv vvvc c  e ACTEL logic gate.C:Gate name:C:Options:"v vv vvvc c  ee ACTEL logic gate.C:Gate name:C:Options:"v vv vvvc c  eee ACTEL logic gate.C:Gate name:C:Options:"vvvv vvvvvvvvc c  e  ACTEL logic gate.C:Gate name:C:Options:#vvv vvvvc c  ee  ACTEL logic gate.C:Gate name:C:Options:#vvvv vvvc c  eee  ACTEL logic gate.C:Gate name:C:Options:#vvvv vvvc c  eee e  ACTEL logic gate.C:Gate name:C:Options:#vvvvvvvvvvvvvc c   e ACTEL logic gate.C:Gate name:C:Options:$vvvvvvvvvvvvvc c   ee ACTEL logic gate.C:Gate name:C:Options:$vvvvvvvvvvvvvc c   eee ACTEL logic gate.C:Gate name:C:Options:$vvvvvvvvc c   eeee ACTEL logic gate.C:Gate name:C:Options:$vvvvvvvvc c   eeee e ACTEL logic gate.C:Gate name:C:Options:$v vvvvc c   c e ACTEL logic gate.C:Gate name:C:Options:"v vvvvv vvc c   ee ACTEL logic gate.C:Gate name:C:Options:"v vvvvv vvc c   eee ACTEL logic gate.C:Gate name:C:Options:"vvvvv vc cc e  ACTEL logic gate.C:Gate name:C:Options:#vvvvv vc c cee  ACTEL logic gate.C:Gate name:C:Options:#vvvvvv c c ce ee ACTEL logic gate.C:Gate name:C:Options:#vvvvvv c c ce ee e ACTEL logic gate.C:Gate name:C:Options:#vvvvvvvvvvvvc c c eACTEL logic gate.C:Gate name:C:Options:$vvvvvvvc c c eeACTEL logic gate.C:Gate name:C:Options:$vvvvvvvc c c eeeACTEL logic gate.C:Gate name:C:Options:$vvvvvvvvvvvvc c c eeeeACTEL logic gate.C:Gate name:C:Options:$vvvvvvvvvvvvc c c ee eeeACTEL logic gate.C:Gate name:C:Options:$    ACTEL logic gate.C:Gate name:C:Options:#    ACTEL logic gate.C:Gate name:C:Options:#    ACTEL logic gate.C:Gate name:C:Options:#    ACTEL logic gate.C:Gate name:C:Options:#        ACTEL logic gate.C:Gate name:C:Options:$        ACTEL logic gate.C:Gate name:C:Options:$      ACTEL logic gate.C:Gate name:C:Options:$      ACTEL logic gate.C:Gate name:C:Options:$      ACTEL logic gate.C:Gate name:C:Options:$v vvv vc c c   ACTEL logic gate.C:Gate name:C:Options:"v vvvv c c c   eACTEL logic gate.C:Gate name:C:Options:"v vvvv c c   c eeACTEL logic gate.C:Gate name:C:Options:"vv vvvv cc c  ACTEL logic gate.C:Gate name:C:Options:#vvv vv vc c ce ACTEL logic gate.C:Gate name:C:Options:#vvv vvv c c cee ACTEL logic gate.C:Gate name:C:Options:#vvv vvv vvvvvc c cee e ACTEL logic gate.C:Gate name:C:Options:#vvvvvvvc c c ACTEL logic gate.C:Gate name:C:Options:$vvvvvvvc c c eACTEL logic gate.C:Gate name:C:Options:$vvvvvvvvvvvvc c c eeACTEL logic gate.C:Gate name:C:Options:$vvvvvvvvvvvvc c c eeeACTEL logic gate.C:Gate name:C:Options:$vvvvvvvvvvvvc c c eeee ACTEL logic gate.C:Gate name:C:Options:$      ACTEL output pad buffer.C:Gate name:C:Options:       ACTEL flip-flop with clear.C:Gate name:C:Options:`À"      ACTEL tri-state output pad buffer.If enable is high, output is driven.C:Gate name:C:Options:     ACTEL logic gate.C:Gate name:C:Options:#    ACTEL logic gate.C:Gate name:C:Options:#         ACTEL logic gate.C:Gate name:C:Options:"    ACTEL logic gate.C:Gate name:C:Options:#    ACTEL logic gate.C:Gate name:C:Options:#      ACTEL logic gate.C:Gate name:C:Options:"ACTEL logic gate.C:Gate name:C:Options:#      ACTEL logic gate.C:Gate name:C:Options:"