/**************************************************************************

SPCimpl.h: This file is a bridge between the OpenSPC library and the
specific SPC core implementation (in this case, SNEeSe's).  As the licensing
rights for SNEeSe are somewhat unclear at this point, none of the files in
this directory are LGPL.  See the SNEeSe documentation for license info for
these files.

 **************************************************************************/

#ifndef SPCIMPL_H
#define SPCIMPL_H

extern unsigned char _SPCRAM[65536],_SPC_DSP[256];
extern unsigned long __SPC_PC,__SPC_SP,_SPC_Cycles,_TotalCycles,
  _Map_Byte,_Map_Address;
extern unsigned short __SPC_YA,_SPC_T0_target,_SPC_T1_target,_SPC_T2_target;
extern unsigned char __SPC_A,__SPC_Y,__SPC_X,__SPC_PSW,
  _SPC_PORT0R,_SPC_PORT1R,_SPC_PORT2R,_SPC_PORT3R,
  _SPC_PORT0W,_SPC_PORT1W,_SPC_PORT2W,_SPC_PORT3W,
  _SPC_T0_counter,_SPC_T1_counter,_SPC_T2_counter,
  _N_flag,_H_flag,_I_flag,_B_flag,_Z_flag,_P_flag,_V_flag,_C_flag;

void _Reset_SPC(void);
void _SPC_START(void);
unsigned char _get_SPC_PSW(void);
void SPC_SetState(int pc,int a,int x,int y,int p,int sp,void *ram);

/* These are ugly ugly nasty evil hacks to let me get at variables that were
   not exported by the original SPC core, but that need to be set properly
   in order to resume a state instead of starting from reset. */
#define SPC_FFC0_Address (*(void **)(&_SPC_T2_target+1))
#define SPC_Code_Base (*(void **)(&__SPC_PC-1))
#define SPC_PAGE (*(long *)(&__SPC_Y+3))

#define SPC_Run(c)\
{\
	_SPC_Cycles+=(c);\
	__asm__("pusha;call _SPC_START;popa");\
}

#define SPC_GetCycles() _TotalCycles

#define SPC_Reset()\
{\
	_Reset_SPC();\
}

#define SPC_RAM _SPCRAM
#define DSPregs _SPC_DSP

#define WritePort0(x) _SPC_PORT0R=x
#define WritePort1(x) _SPC_PORT1R=x
#define WritePort2(x) _SPC_PORT2R=x
#define WritePort3(x) _SPC_PORT3R=x

#define ReadPort0() _SPC_PORT0W
#define ReadPort1() _SPC_PORT1W
#define ReadPort2() _SPC_PORT2W
#define ReadPort3() _SPC_PORT3W

#endif /* #ifndef SPCIMPL_H */